PIC16C925/CL Microchip Technology, PIC16C925/CL Datasheet - Page 53

• Manufacturer Part Number: PIC16C925/CL
• Description: IC MCU EPROM 4KX14 LCDDVR 68CLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C925/CL

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: EPROM
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-CLCC Window, 68-CERQUAD
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA16XL680 - ADAPTER DEVICE FOR MPLAB-ICEAC164024 - ADAPTER PICSTART PLUS 68PLCCAC164022 - MODULE SKT PROMATEII 68PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.0
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module. It can also be used
as a time-base for the Master mode SPI clock. The
TMR2 register is readable and writable, and is cleared
on any device RESET.
The input clock (F
1:4,
T2CKPS1:T2CKPS0 (T2CON<1:0>)).
The Timer2 module has an 8-bit period register, PR2.
TMR2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
set during RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 7-1 shows the Timer2 control register.
2001 Microchip Technology Inc.
or
TIMER2 MODULE
1:16
OSC
(selected
/4) has a prescale option of 1:1,
by
control
Preliminary
bits
7.1
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
TMR2 will not clear when T2CON is written.
7.2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate the shift clock.
FIGURE 7-1:
F
Note 1: TMR2 register output can be software selected by the
Reset, or Watchdog Timer Reset)
OSC
/4
Timer2 Prescaler and Postscaler
Output of TMR2
SSP Module as the source clock.
1:1, 1:4, 1:16
Prescaler
2
PIC16C925/926
TIMER2 BLOCK DIAGRAM
Comparator
TMR2 reg
PR2 reg
TMR2
Output
RESET
EQ
DS39544A-page 51
(1)
1:16
Postscaler
4
Sets Flag
bit TMR2IF
to
1:1