PIC16C925/CL Microchip Technology, PIC16C925/CL Datasheet - Page 119

• Manufacturer Part Number: PIC16C925/CL
• Description: IC MCU EPROM 4KX14 LCDDVR 68CLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C925/CL

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: EPROM
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-CLCC Window, 68-CERQUAD
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA16XL680 - ADAPTER DEVICE FOR MPLAB-ICEAC164024 - ADAPTER PICSTART PLUS 68PLCCAC164022 - MODULE SKT PROMATEII 68PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
Before Instruction:
After Instruction:
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
Before Instruction:
After Instruction:
2001 Microchip Technology Inc.
FLAG_REG =
FLAG_REG =
FLAG_REG =
FLAG_REG =
Bit Clear f
[ label ] BCF
0
0
0
None
Bit ’b’ in register ’f’ is cleared.
1
1
BCF
Bit Set f
[ label ] BSF
0
0
1
None
Bit ’b’ in register ’f’ is set.
1
1
BSF
Decode
Decode
Q1
Q1
01
01
f
b
f
b
(f<b>)
(f<b>)
127
127
7
7
0x0A
0x8A
0xC7
0x47
FLAG_REG,
register
register
00bb
Read
01bb
Read
FLAG_REG, 7
Q2
Q2
’f’
’f’
f [,b]
f [,b]
Process
Process
bfff
bfff
data
data
Q3
Q3
7
register ’f’
register ’f’
ffff
Write
ffff
Write
Q4
Q4
Preliminary
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example
Before Instruction:
After Instruction:
If Skip:
PC
if FLAG<1> =
PC
if FLAG<1> =
PC
PIC16C925/926
=
Bit Test, Skip if Clear
[ label ] BTFSC f [,b]
0
0
skip if (f<b>) = 0
None
If bit ’b’ in register ’f’ is ’1’, then the
next instruction is executed.
If bit ’b’ in register ’f’ is ’0’, then the
next instruction is discarded, and a
NOP is executed instead, making this a
2T
1
1(2)
HERE
FALSE
TRUE
(2nd Cycle)
Operation
Decode
CY
Q1
Q1
address HERE
=
=
01
No
f
b
instruction.
127
7
0,
address TRUE
1,
address FALSE
BTFSC
GOTO
•
•
•
register ’f’
Operation
10bb
Read
Q2
Q2
No
DS39544A-page 117
FLAG,1
PROCESS_CODE
Operation
Process
bfff
data
Q3
Q3
No
Operation
Operation
ffff
Q4
Q4
No
No