PIC18C658/CL Microchip Technology, PIC18C658/CL Datasheet - Page 280
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C658/CL
Manufacturer Part Number
PIC18C658/CL
Description
IC MCU OTP 16KX16 CAN 68-PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658/CL
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
Q1068347
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 280 of 366
- Download datasheet (7Mb)
PIC18CXX8
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example1:
Example 2:
DS30475A-page 280
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
Q1
WREG
C
DC
WREG
C
DC
WREG
C
DC
WREG
C
DC
register WREG
=
=
=
=
=
=
=
=
=
=
=
=
Decimal Adjust WREG Register
[label] DAW
None
If [WREG<3:0> >9] or [DC = 1]
then
(WREG<3:0>) + 6
else
(
If [WREG<7:4> >9] or [C = 1] then
(
else
(WREG<7:4>)
C
DAW adjusts the eight bit value in
WREG resulting from the earlier
addition of two variables (each in
packed BCD format) and produces
a correct packed BCD result.
1
1
DAW
Read
WREG<3:0>)
WREG<7:4>) + 6
Q2
0000
0xA5
0
0
0x05
1
0
0xCE
0
0
0x34
1
0
0000
Process
Data
Q3
WREG<7:4>;
W<3:0>;
0000
W<3:0>;
WREG<7:4>;
Advanced Information
WREG
Write
Q4
0111
DECF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
CNT
Z
CNT
Z
Q1
=
=
=
=
register ’f’
Decrement f
[ label ] DECF f [ ,d [,a] ]
0
d
a
(f) – 1
C,DC,N,OV,Z
Decrement register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
1
1
DECF
Read
0000
Q2
0x01
0
0x00
1
f
[0,1]
[0,1]
2000 Microchip Technology Inc.
255
dest
CNT
01da
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
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