PIC16LC61-04I/P Microchip Technology, PIC16LC61-04I/P Datasheet - Page 54

• Manufacturer Part Number: PIC16LC61-04I/P
• Description: MICR CTL LP 1K 4MHZ OTP ET 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC61-04I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PIC16C6X
FIGURE 5-4:
TABLE 5-3:
TABLE 5-4:
DS30234D-page 54
Name
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Address
06h, 106h PORTB
86h, 186h TRISB
81h, 181h OPTION
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
Data bus
Note 1: I/O pins have diode protection to V
WR Port
WR TRIS
RBPU
RB7:RB6 in serial programming mode
Set RBIF
From other
RB7:RB4 pins
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
(2)
and clear the RPBU bit (OPTION<7>).
Name
RD TRIS
RD Port
Bit#
Data Latch
TRIS Latch
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
BLOCK DIAGRAM OF THE
RB7:RB4 PINS FOR
PIC16C62A/63/R63/64A/65A/
R65/66/67
D
D
PORTB FUNCTIONS
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
CK
CK
PORTB Data Direction Register
RBPU
Bit 7
RB7
Q
Q
Buffer Type
TTL/ST
TTL/ST
TTL/ST
INTEDG
TTL
TTL
TTL
TTL
TTL
Bit 6
Q
RB6
Q
Latch
DD
(1)
(2)
(2)
EN
EN
D
and V
D
TTL
Input
Buffer
T0CS
Bit 5
RB5
SS
Input/output pin or external interrupt input. Internal software programmable
weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
V
Function
P
.
DD
ST
Buffer
weak
pull-up
RD Port
I/O
pin
Q1
T0SE
Q3
Bit 4
RB4
(1)
Bit 3
PSA
RB3
FIGURE 5-5:
Data bus
WR TRIS
WR Port
RBPU
RB0/INT
Note 1: I/O pins have diode protection to V
Bit 2
RB2
PS2
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
(2)
and clear the RPBU bit (OPTION<7>).
Bit 1
RB1
PS1
BLOCK DIAGRAM OF THE
RB3:RB0 PINS
Bit 0
RB0
RD TRIS
RD Port
PS0
TRIS Latch
Data Latch
D
D
CK
CK
Schmitt Trigger
Buffer
1997 Microchip Technology Inc.
Q
Q
xxxx xxxx uuuu uuuuu
1111 1111
1111 1111
Value on:
POR,
BOR
Q
DD
and V
EN
other resets
TTL
Input
Buffer
Value on all
1111 1111
1111 1111
D
SS
.
V
P
RD Port
DD
weak
pull-up
I/O
pin
(1)