PIC16LC61-04I/P Microchip Technology, PIC16LC61-04I/P Datasheet - Page 53

• Manufacturer Part Number: PIC16LC61-04I/P
• Description: MICR CTL LP 1K 4MHZ OTP ET 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC61-04I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

5.2
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance mode. Clearing a bit in the
TRISB register puts the contents of the output latch on
the selected pin(s).
EXAMPLE 5-2:
BCF
CLRF
BSF
MOVLW
MOVWF
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are also
disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB port change
interrupt with flag bit RBIF (INTCON<0>).
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1997 Microchip Technology Inc.
STATUS, RP0
PORTB
STATUS, RP0
0xCF
TRISB
PORTB and TRISB Register
INITIALIZING PORTB
;
; Initialize PORTB by
; clearing output
; data latches
; Select Bank 1
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on these four pins allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, Application Note, “Implementing
Wake-up on Key Stroke” (AN552) .
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-3:
Set RBIF
Note:
Data bus
Note 1: I/O pins have diode protection to V
WR TRIS
WR Port
RBPU
RB7:RB6 in serial programming mode
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
(2)
From other
RB7:RB4 pins
and clear the RPBU bit (OPTION<7>).
For PIC16C61/62/64/65, if a change on the
I/O pin should occur when a read operation
is being executed (start of the Q2 cycle),
then interrupt flag bit RBIF may not get set.
BLOCK DIAGRAM OF THE
RB7:RB4 PINS FOR
PIC16C61/62/64/65
RD TRIS
RD Port
Data Latch
TRIS Latch
D
D
CK
CK
Q
Q
PIC16C6X
Q
Q
Latch
DD
DS30234D-page 53
EN
EN
D
and V
D
TTL
Input
Buffer
SS
V
RD Port
P
.
DD
ST
Buffer
weak
pull-up
I/O
pin
(1)