PIC16LC61-04I/P Microchip Technology, PIC16LC61-04I/P Datasheet - Page 23

• Manufacturer Part Number: PIC16LC61-04I/P
• Description: MICR CTL LP 1K 4MHZ OTP ET 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC61-04I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

4.2.2
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
Address Name
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented locations read as '0'.
Note 1: These registers can be addressed from either bank.
Bank 1
1997 Microchip Technology Inc.
Bank 0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1,2)
(1)
(1,2)
(1)
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose con-
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
SPECIAL FUNCTION REGISTERS:
Shaded locations are unimplemented and read as ‘0’
tents are transferred to the upper byte of the program counter. (PC<12:8>)
—
—
—
–
–
–
SPECIAL FUNCTION REGISTERS FOR THE PIC16C61
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Control Register
Unimplemented
Unimplemented
Unimplemented
IRP
RBPU
IRP
Bit 7
GIE
GIE
—
—
—
—
(4)
(4)
INTEDG
RP1
RP1
Bit 6
—
—
—
—
—
—
(4)
(4)
T0CS
Bit 5
T0IE
T0IE
RP0
RP0
—
—
—
—
PORTA Data Latch when written: PORTA pins when read
Write Buffer for the upper 5 bits of the Program Counter
PORTA Data Direction Register
Write Buffer for the upper 5 bits of the Program Counter
T0SE
INTE
INTE
Bit 4
TO
TO
RBIE
RBIE
Bit 3
PSA
PD
PD
The special function registers can be classified into two
sets (core and peripheral). The registers associated
with the “core” functions are described in this section
and those related to the operation of the peripheral fea-
tures are described in the section of that peripheral fea-
ture.
Bit 2
T0IF
T0IF
PS2
Z
Z
Bit 1
INTF
INTF
PS1
DC
DC
RBIF
RBIF
Bit 0
PS0
C
C
PIC16C6X
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0-00 000x 0-00 000u
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
---1 1111 ---1 1111
1111 1111 1111 1111
---0 0000 ---0 0000
0-00 000x
Value on:
DS30234D-page 23
POR
—
—
—
—
—
—
0-00 000u
Value on
all other
resets
—
—
—
—
—
—
(3)