PIC16LC61-04I/P Microchip Technology, PIC16LC61-04I/P Datasheet - Page 20

• Manufacturer Part Number: PIC16LC61-04I/P
• Description: MICR CTL LP 1K 4MHZ OTP ET 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC61-04I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PIC16C6X
FIGURE 4-4:
4.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1:RP0 (STATUS<6:5>)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
4.2.1
These registers are accessed either directly or indi-
rectly through the File Select Register (FSR)
(Section 4.5).
DS30234D-page 20
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
= 00
= 01
= 10
= 11
CALL, RETURN
RETFIE, RETLW
Data Memory Organization
GENERAL PURPOSE REGISTERS
Bank0
Bank1
Bank2
Bank3
Peripheral Interrupt Vector
PIC16C66/67 PROGRAM
MEMORY MAP AND STACK
On-chip Program
Memory (Page 0)
On-chip Program
Memory (Page 1)
On-chip Program
Memory (Page 2)
On-chip Program
Memory (Page 3)
Stack Level 1
Stack Level 8
Reset Vector
PC<12:0>
13
0005h
0000h
0004h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
For the PIC16C61, general purpose register locations
8Ch-AFh of Bank 1 are not physically implemented.
These locations are mapped into 0Ch-2Fh of Bank 0.
FIGURE 4-5:
File Address
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
2Fh
30h
7Fh
2: These locations are unimplemented in
Bank 1. Any access to these locations will
access the corresponding Bank 0 register.
PCLATH
INTCON
STATUS
Purpose
Register
General
PORTA
PORTB
INDF
Bank 0
TMR0
PIC16C61 REGISTER FILE
MAP
FSR
PCL
(1)
1997 Microchip Technology Inc.
in Bank 0
OPTION
STATUS
PCLATH
INTCON
Mapped
INDF
Bank 1
TRISA
TRISB
PCL
FSR
(1)
(2)
File Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
AFh
B0h
FFh