PIC16LC61-04I/P Microchip Technology, PIC16LC61-04I/P Datasheet - Page 136

• Manufacturer Part Number: PIC16LC61-04I/P
• Description: MICR CTL LP 1K 4MHZ OTP ET 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC61-04I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PIC16C6X
13.5
The PIC16C6X family has up to 11 sources of interrupt.
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Global interrupt enable bit, GIE (INTCON<7>) enables
(if set) all un-masked interrupts or disables (if cleared)
all interrupts. When bit GIE is enabled, and an interrupt
flag bit and mask bit are set, the interrupt will vector
immediately. Individual interrupts can be disabled
through their corresponding enable bits in the INTCON
register. GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enable interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flag bits are contained
in the INTCON register.
The peripheral interrupt flag bits are contained in spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2 and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, bit GIE is cleared to
disable any further interrupts, the return address is
pushed onto the stack and the PC is loaded with
0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the RB0/INT pin
or RB port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs
19). The latency is the same for one or two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
DS30234D-page 136
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Note:
Interrupts
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or global enable bit, GIE.
(Figure 13-
avoid infinite interrupt requests. Individual interrupt flag
bits are set regardless of the status of their correspond-
ing mask bit or the GIE bit.
Note:
LOOP BCF INTCON,GIE
BTFSC INTCON,GIE
GOTO
:
For the PIC16C61/62/64/65, if an interrupt
occurs while the Global Interrupt Enable
bit, GIE is being cleared, bit GIE may unin-
tentionally be re-enabled by the user’s
Interrupt Service Routine (the RETFIE
instruction). The events that would cause
this to occur are:
1.
2.
3.
4.
LOOP
An instruction clears the GIE bit while
an interrupt is acknowledged
The program branches to the Interrupt
vector and executes the Interrupt Ser-
vice Routine.
The Interrupt Service Routine com-
pletes with the execution of the RET-
FIE instruction. This causes the GIE
bit to be set (enables interrupts), and
the program returns to the instruction
after the one which was meant to dis-
able interrupts.
Perform the following to ensure that
interrupts are globally disabled.
1997 Microchip Technology Inc.
;Disable Global
;Interrupt bit
;Global Interrupt
;Disabled?
;NO, try again
;Yes, continue
;with program flow