SAF-TC1167-128F133HL AD Infineon Technologies, SAF-TC1167-128F133HL AD Datasheet - Page 38
SAF-TC1167-128F133HL AD
Manufacturer Part Number
SAF-TC1167-128F133HL AD
Description
IC MCU 32BIT FLASH 176-LQFP
Manufacturer
Infineon Technologies
Series
TC116xr
Specifications of SAF-TC1167-128F133HL AD
Core Processor
TriCore
Core Size
32-Bit
Speed
133MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
88
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 32x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFQFP
Data Bus Width
32 bit
Data Ram Size
104 KB
Interface Type
ASC, MLI, MSC, SSC
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
88
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (12 bit, 16 Channel) / 10 bit, 4 Channel
Packages
PG-LQFP-176
Max Clock Frequency
133.0 MHz
Sram (incl. Cache)
128.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
36
Program Memory
1.0 MB
For Use With
B158-H8690-X-0-7600IN - KIT STARTER TC116X SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
SP000602800
Features
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2.4.3
The Micro Second Channel (MSC) interface provides serial communication links
typically used to connect power switches or other peripheral devices. The serial
communication link includes a fast synchronous downstream channel and a slow
asynchronous upstream channel.
of the MSC interface.
Data Sheet
Master and Slave Mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: Idle low or idle high state for the shift clock
– Programmable clock/data phase: Data shift with leading or trailing edge of the shift
Baud rate generation
– Master Mode: 40.0 Mbit/s to 610.36 bit/s (@ 80 MHz module clock)
– Slave Mode: 20 Mbit/s to 610.36 bit/s (@ 80 MHz module clock)
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Flexible SSC pin configuration
Seven slave select inputs SLSI[7:1] in Slave Mode
Eight programmable slave select outputs SLSO in Master Mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
clock
Micro Second Channel Interface
Figure 7
34
shows a global view of the interface signals
Introduction
V1.3, 2009-10
TC1167