SAF-TC1167-128F133HL AD Infineon Technologies, SAF-TC1167-128F133HL AD Datasheet - Page 114

• Manufacturer Part Number: SAF-TC1167-128F133HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1167-128F133HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 104 KB
• Interface Type: ASC, MLI, MSC, SSC
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel) / 10 bit, 4 Channel
• Packages: PG-LQFP-176
• Max Clock Frequency: 133.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• For Use With: B158-H8690-X-0-7600IN - KIT STARTER TC116X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000602800

5.3.6
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
Table 20
Parameter
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
TDO valid after TCK falling
edge
TDO hold after TCK falling
edge
TDO high imped. to valid
from TCK falling edge
TDO valid to high imped.
from TCK falling edge
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
1)
1)
characterization.
(propagation delay)
JTAG Interface Timing
JTAG Interface Timing Parameters
(Operating Conditions apply)
1)2)
1)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
8
18
9
10
SR
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
Min.
25
12
10
–
–
6
6
–
–
2
–
–
109
Values
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
Max.
–
–
–
4
4
–
–
13
3
–
14
13.5
Unit Note /
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Electrical Parameters
Test Condition
–
–
–
–
–
–
–
C
C
C
C
L
L
L
L
= 50 pF
= 20 pF
= 50 pF
= 50 pF
V1.3, 2009-10
TC1167