SAF-TC1167-128F133HL AD Infineon Technologies, SAF-TC1167-128F133HL AD Datasheet - Page 112

• Manufacturer Part Number: SAF-TC1167-128F133HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1167-128F133HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 104 KB
• Interface Type: ASC, MLI, MSC, SSC
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel) / 10 bit, 4 Channel
• Packages: PG-LQFP-176
• Max Clock Frequency: 133.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• For Use With: B158-H8690-X-0-7600IN - KIT STARTER TC116X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000602800

With rising number
of
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency
Figure 26
Figure 26
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
Data Sheet
Dm
m
that is defined by the K2-factor of the PLL. Beyond this value of
±10.0
±8.0
±7.0
±6.0
±4.0
±2.0
±1.0
±0.0
not exceed
applications with many pins with high loads, driver strengths and toggle rates the
specified jitter values could be exceeded.
V
V
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply votage, measured between
V
V
frequencies above 300 KHz.
ns
DDOSC3
PP
DDOSC
PP
0
D m
m
K2
= 100 mV for noise frequencies below 300 KHz and
= 100 mV for noise frequencies below 300 KHz and
f
gives the jitter curves for several K2 /
LMB
= M ax . jitter
= N um ber of c ons ec utiv e f
= K2- div ider of PLL
at pin 105 and
Approximated Maximum Accumulated PLL Jitter for Typical LMB-
Bus Clock Frequencies
at pin 106 and
results in a higher absolute maximum jitter value.
f
LMB
C
20
m
= 40 M H z (K 2 = 10 )
L
f
LMB
of clock cycles the maximum jitter increases linearly up to a value
= 20 pF with the maximum driver and sharp edge. In case of
= 133 M H z (K2 = 6 )
LMB
V
40
V
periods
SSOSC
f
SSOSC
LMB
= 40 M H z (K2 = 20)
f
f
LMB
LMB
at pin 104, is limited to a peak-to-peak voltage of
at pin 104, is limited to a peak-to-peak voltage of
= 80 M H z (K2 = 10 )
= 80 M H z (K2 = 6)
f
60
LMB
107
f
LMB
80
combinations.
100
Electrical Parameters
V
V
PP
PP
= 40 mV for noise
= 40 mV for noise
m
T C 1167 _PLL _J IT T_C
120
the maximum
V1.3, 2009-10
TC1167
o
m
o