SAF-TC1130-L150EB-G BB Infineon Technologies, SAF-TC1130-L150EB-G BB Datasheet - Page 64

• Manufacturer Part Number: SAF-TC1130-L150EB-G BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB-G BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 144 KB
• Interface Type: 3xASC, 2xSSC, I2C, 2xMLI, Ethernet 10, 100 Mbits, s, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 9
• Operating Supply Voltage: 1.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-LBGA-208
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 144.0 KByte
• Can Nodes: 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: FT1130L150EBGBBXP; SAF-TC1130-L150EB-GBB; SAF-TC1130-L150EB-GBBINTR; SAF-TC1130-L150EB-GBBTR; SAF-TC1130-L150EB-GBBTR; SAFTC1130L150EBBBXT; SP000106119; SP000106538; SP000743584

3.18
The STM within the TC1130 is designed for global system timing applications requiring
both high precision and long range. The STM provides the following features:
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Flexible interrupt generation on partial STM content compare match
• Driven by clock
• Counting starts automatically after a reset operation
• STM is reset under following reset causes:
• STM (and the clock divider) is not reset at watchdog reset and hardware reset
The STM is an upward counter, running with the system clock frequency
f
Other than via reset, it is not possible to affect the contents of the timer during normal
operation of the application; it can only be read, but not written to. Depending on the
implementation of the clock control of the STM, the timer can optionally be disabled or
suspended for power-saving and debugging purposes via a clock control register.
The maximum clock period is 2
STM counts 15.2 years before overflowing. Thus, it is capable of continuously timing the
entire expected product lifetime of a system without overflowing.
Data Sheet
STM
(HDRST = 0)
– Wake-up reset (PMG_CON.DSRW must be set)
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
=
f
SYS
System Timer
). It is enabled per default after reset, and immediately starts counting up.
f
STM
after reset (default after reset is
56
/
f
STM
. At
f
58
STM
= 150 MHz (maximum), for example, the
f
STM
=
Functional Description
f
SYS
= 150 MHz)
f
SYS
V1.1, 2008-12
(after reset
TC1130