SAF-TC1130-L150EB-G BB Infineon Technologies, SAF-TC1130-L150EB-G BB Datasheet - Page 63

• Manufacturer Part Number: SAF-TC1130-L150EB-G BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB-G BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 144 KB
• Interface Type: 3xASC, 2xSSC, I2C, 2xMLI, Ethernet 10, 100 Mbits, s, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 9
• Operating Supply Voltage: 1.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-LBGA-208
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 144.0 KByte
• Can Nodes: 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: FT1130L150EBGBBXP; SAF-TC1130-L150EB-GBB; SAF-TC1130-L150EB-GBBINTR; SAF-TC1130-L150EB-GBBTR; SAF-TC1130-L150EB-GBBTR; SAFTC1130L150EBBBXT; SP000106119; SP000106538; SP000743584

TC1130
Functional Description
RB and TB provide on-chip data buffering whereas DMUR and DMUT perform data
transfer from/to the shared memory.
Two interfaces are provided by the Ethernet Controller module:
• MII interface for connection of Ethernet PHYs via 18 Input/Output lines
• Master/slave FPI bus interface for connection to the on-chip system bus for data
transfer as well as configuration
Features:
• Media Independent Interface (MII) according to IEEE 802.3
• Supports 10 or 100 Mbit/sec MII-based Physical devices
• Supports Full Duplex Ethernet
• Supports data transfer between Ethernet Controller and COM-DRAM
• Supports data transfer between Ethernet Controller and SDRAM via EBU
• 256 x 32 bit Receive buffer and Transmit buffer each
• Supports burst transfers up to 8 x 32 Bytes
Media Access Controller (MAC)
• 100/10 Mbit/sec operations
• Full IEEE 802.3 compliance
• Station management signaling
• Large on-chip CAM (Content Addressable Memory)
• Full duplex mode
• 80-byte transmit FIFO
• 16-byte receive FIFO
• PAUSE Operation
• Flexible MAC Control Support
• Supports Long Packet mode and Short Packet mode
• PAD generation
Media Independent Interface (MII)
• Media independence
• Multi-vendor point of interoperability
• Supports connection of MAC layer and Physical (PHY) layer devices
• Capable of supporting both 100 Mbit/sec and 10 Mbit/sec data rates
• Data and delimiters are synchronous to clock references
• Provides independent four bits wide transmit and receive data paths
• Supports connection of PHY layer and Station Management (STA) devices
• Provides a simple management interface
• Capable of driving a limited length of shielded cable
Data Sheet
57
V1.1, 2008-12