SAK-TC1736-128F80HL AA Infineon Technologies, SAK-TC1736-128F80HL AA Datasheet - Page 55

• Manufacturer Part Number: SAK-TC1736-128F80HL AA
• Description: IC MCU 32BIT 1MB FLASH 144LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1736-128F80HL AA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 70
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Packages: PG-LQFP-144
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 48.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.6
The TC1736 contains resources for different kinds of “debugging”, covering needs from
software development to real-time-tuning. These resources are either embedded in
specific modules (e.g. breakpoint logic of the TriCore) or part of a central peripheral
(known as CERBERUS).
2.6.1
The classic software debug approach (start/stop, single-stepping) is supported by
several features labelled “OCDS Level 1”:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.6.2
For detailed tracing of the system’s behavior a pin-compatible Emulation Device will be
available.
1) The OCDS L2 interface of AudoNG is not available.
Data Sheet
Run/stop and single-step execution for TriCore.
Means to request all kinds of reset without usage of sideband pins.
Halt-after-Reset for repeatable debug sessions.
Different Boot modes to use application software not yet programmed to the Flash.
A total of four hardware breakpoints for the TriCore based on instruction address,
data address or combination of both.
Unlimited number of software breakpoints (DEBUG instruction) for TriCore.
Debug event generated by access to a specific address via the system peripheral
bus.
Tool access to all SFRs and internal memories independent of the Core.
Two central Break Switches to collect debug events from all modules (TriCore, DMA,
BCU, break input pins) and distribute them selectively to breakable modules
(TriCore, break output pins).
Central Suspend Switch to suspend parts of the system (TriCore, Peripherals)
instead if breaking them as reaction to a debug event.
Dedicated interrupt resources to handle debug events inside TriCore (breakpoint
trap, software interrupt) and Cerberus, e.g. for implementing Monitor programs.
Access to all OCDS Level 1 resources also for TriCore for debug tools integrated into
the application code.
Triggered Transfer of data in response to a debug event; if target is programmed to
be a device interface simple variable tracing can be done.
In depth performance analysis and profiling support given by the Emulation Device
through MCDS Event Counters driven by a variety of trigger signals (e.g. cache hit,
wait state, interrupt accepted).
1)
On-Chip Debug Support (OCDS)
On-Chip Debug Support
Real Time Trace
51
Introduction
V1.1, 2009-08
TC1736