SAK-TC1736-128F80HL AA Infineon Technologies, SAK-TC1736-128F80HL AA Datasheet - Page 106

• Manufacturer Part Number: SAK-TC1736-128F80HL AA
• Description: IC MCU 32BIT 1MB FLASH 144LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1736-128F80HL AA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 70
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Packages: PG-LQFP-144
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 48.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2)
3) Any ESR0 activation is internally prolonged to SCU_RSTCNTCON.RELSA FPI bus clock (
4) Applicable for input pins TESTMODE and TRST pins.
5)
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
9) The duration of the boot time is defined between the following events:
Figure 9
Data Sheet
TESTMODE
t
0,3 ×
optimized by the customer and checked for negative resistance as recommended and specified by crystal
suppliers.
f
user instruction has entered the CPU and its processing starts.
1. Hardware reset: the falling edge of a short ESR0 pulse and the moment when the first user instruction has
entered
SCU_RSTCNTCON.RELSA ×
If the ESR0 pulse is longer than SCU_RSTCNTCON.RELSA ×
to the boot time (ESR0 falling edge to first user instruction).
2. Software reset: the moment of starting the software reset and the moment when the first user instruction
has entered the CPU and its processing starts
OSCS
FPI
HWCFG
PORST
=
VDDP
TRST
ESR0
Pads
VDD
is defined from the moment when
V
f
CPU
DDOSC3
V
D D PPA
/ 2
the
. This parameter is verified by device characterization. The external oscillator circuitry must be
Power, Pad and Reset Timing
Pad-state undefined
Tri-state or pull device active
As programmed
CPU
t
POA
t
POA
and
t
hd
t
PIP
T
t
POH
its
FPI
t
t
HDH
PI
.
processing
V
DDOSC3
t
PIP
= 3.13 V until the oscillations reach an amplitude at XTAL1 of
t
PI
102
starts,
t
hd
t
PIP
if
t
POH
t
t
HDH
PI
T
FPI
the
, only the time beyond it should be added
ESR0
t
t
HDH
PI
Electrical Parameters
pulse
t
PI
V
D D
-12%
is
f
FPI
V1.1, 2009-08
) cycles.
shorter
V
TC1736
D D P
V
reset_beh2
D D PPA
-12%
than