SAK-TC1736-128F80HL AA Infineon Technologies, SAK-TC1736-128F80HL AA Datasheet
SAK-TC1736-128F80HL AA
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SAK-TC1736-128F80HL AA Summary of contents
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TC1736 32-Bit Single-Chip Microcontroller Data Sheet V1.1 2009- ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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TC1736 32-Bit Single-Chip Microcontroller Data Sheet V1.1 2009- ...
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... Page 5-103 The notes under the PLL sections are updated. Trademarks TriCore® trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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On-Chip Debug Support (OCDS 2.6.1 On-Chip Debug ...
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Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Summary of Features • High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – MHz operation ...
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A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) • 70 digital general purpose I/O lines (GPIO), 4 input lines • Digital I/O ports with 3.3 V capability • On-chip ...
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... For the available ordering codes for the TC1736 please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants. This document describes the derivatives of the device.The derivatives and summarizes the differences. Table 1 TC1736 Derivative Synopsis Derivative SAK-TC1736-128F80HL SAK-TC1736-96F40HL Data Sheet Ambient PFlash Temperature Range ...
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Introduction The TC1736 32-Bit Single-Chip Microcontroller is a cost-optimized version of the TC1767 32-Bit Single-Chip Microcontroller with less pin count and less functionalities. In comparison to the TC1767, the TC1736 provides: • Less memories in general • No PCP ...
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Text Conventions This document uses the following text conventions for named components of the TC1736: • Functional units of the TC1736 are given in plain UPPER CASE. For example: “The SSC supports full-duplex and half-duplex synchronous communication”. • Pins ...
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MBaud/Mbit are 1000000 characters/bits per second, and 1 MHz is 1,000,000 Hz. • Data format quantities are defined as follows: – Byte = 8-bit quantity – Half-word = 16-bit quantity – Word = 32-bit quantity – Double-word ...
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Table 2-1 Bit Function Terminology (cont’d) Function of Bits Description s Bits with this attribute are “sticky” in one direction. If their reset value is once overwritten by software, they can be switched again into their reset state only by ...
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Abbreviations and Acronyms The following acronyms and terms are used in this document: ADC Analog-to-Digital Converter AGPR Address General Purpose Register ALU Arithmetic and Logic Unit ASC Asynchronous/Synchronous Serial Controller BCU Bus Control Unit BROM Boot ROM & Test ...
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ICACHE Instruction Cache I/O Input / Output JTAG Joint Test Action Group = IEEE1149.1 LBCU Local Memory Bus Control Unit LDRAM Local Data RAM LFI Local Memory-to-FPI Bus Interface LMB Local Memory Bus LTC Local Timer Cell MLI Micro Link ...
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STM System Timer WDT Watchdog Timer 2.2 System Architecture of the TC1736 The TC1736 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: • Reduced Instruction Set Computing (RISC) processor ...
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Block Diagram Figure 2-1 shows the block diagram of the TC1736. PMI 8 KB SPRAM/ ICACHE (configurable ) Local Memory Bus (LMB) LBCU PMU PFLASH 32 KB DFLASH 16 KB BROM 4 KB OVRAM GPTA ...
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System Features of the The TC1736 has the following features: Packages • PG-LQFP-144-10 package, 0.5 mm pitch Clock Frequencies • Maximum CPU clock frequency: 80 MHz • Maximum SPB clock frequency: 80 MHz Data Sheet TC1736 device 15 TC1736 ...
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High-Performance 32-Bit TriCore CPU TriCore (TC1.3.1) Architectural Highlights • Unified RISC MCU/DSP • 32-bit architecture with 4 Gbytes unified data, program, and input/output address space • Fast automatic context-switching • Multiply-accumulate unit • Floating point unit • Saturating integer ...
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On-Chip System Units The TC1736 32-Bit Single-Chip Microcontroller offers several versatile on-chip system peripheral units such as DMA controller, embedded Flash module, interrupt system and ports. 2.4.1 Flexible Interrupt System The TC1736 includes a programmable interrupt system with the ...
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Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit • Register set for each DMA channel – Source and destination address register – Channel control and status register – Transfer count register • Flexible interrupt generation (the service ...
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System Timer The TC1736’s STM is designed for global system timing applications requiring both high precision and long range. Features • Free-running 56-bit counter • All 56 bits can be read synchronously • Different 32-bit portions of the 56-bit ...
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STM with the STM_CMP0 or STM_CMP1 registers. Figure 2-2 provides an overview on the STM module. It shows the options for reading parts of STM content. to DMA etc. STM IR0 ...
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System Control Unit The following SCU introduction gives an overview about the TC1736 System Control Unit (SCU). 2.4.4.1 Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1736. During user program execution ...
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There are two basic types of reset request triggers: • Trigger sources that do not depend on a clock, such as the PORST. This trigger force the device into an asynchronous reset assertion independently of any clock. The activation of ...
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General Purpose I/O Ports and Peripheral I/O Lines The TC1736 includes a flexible Ports structure with the following features: Features • 70 digital General-Purpose Input/Output (GPIO) port lines • Input/output functionality individually programmable for each port line • Programmable ...
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The following figure shows the block diagram of the PMU0: PMU0 Overlay RAM Interface 64 OVRAM Emulation Memory Interface Emulation Memory (ED chip only ) Figure 2-3 PMU0 Basic Block Diagram 2.4.6.1 Boot ROM The internal 16 Kbyte Boot ROM ...
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For online data acquisition (OLDA) of application or calibration data a virtual 32 KB memory range is provided which can be accessed without error reporting. Accesses to this OLDA range can also be redirected to an overlay memory. 2.4.6.3 Emulation ...
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The minimum programming width is the page, including 256 bytes in Program Flash and 128 bytes in Data Flash. Concurrent programming and erasing in Data Flash is performed using an automatic erase suspend and resume function. A basic block diagram ...
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Dynamic correction of single-bit errors during read access. • Transfer rate in burst mode: One 64-bit double-word per clock cycle. • Sector architecture: – Eight 16 Kbyte, one 128 Kbyte and three 256 Kbyte sectors. – Each sector separately ...
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Operational control per command sequences (unlock sequences, same as those of Program Flash) for protection against unintended operation. • End-of-busy as well as error reporting with interrupt and bus error trap. • Write state machine for automatic program and ...
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Data Access Overlay The data overlay functionality provides the capability to redirect data accesses by the TriCore to program memory (internal Program Flash or external memory) to the Overlay SRAM in the PMU the Emulation Memory in ...
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TC1736 Development Support Overview about the TC1736 development environment: Complete Development Support A variety of software and hardware development tools for the 32-bit microcontroller TC1736 are available from experienced international tool suppliers. The development environment for the Infineon 32-bit ...
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On-Chip Peripheral Units The TC1736 micro controller offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the TC1736 ports are reserved for these peripheral units to communicate with the ...
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Asynchronous/Synchronous Serial Interfaces The TC1736 includes two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1. Both ASC modules have the same functionality. Figure 2-5 shows a global view of the Asynchronous/Synchronous Serial Interface (ASC). f Clock ASC Control Address Decoder EIR ...
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Features • Full-duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity-bit generation/checking – One or two stop bits – Baud rate from 5.0 Mbit/s to 1.19 bit MHz module clock) – Multiprocessor mode ...
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High-Speed Synchronous Serial Interfaces The TC1736 includes two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1. Both SSC modules have the same functionality. Figure 2-6 shows a global view of the Synchronous Serial interface (SSC). f SSC Clock f Control ...
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Features • Master and Slave Mode operation – Full-duplex or half-duplex operation – Automatic pad control possible • Flexible data format – Programmable number of data bits bits – Programmable shift direction: LSB or MSB shift first ...
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Micro Second Channel Interface The Micro Second Channel (MSC) interface provides serial communication links typically used to connect power switches or other peripheral devices. The serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream ...
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Features • Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses • High-speed synchronous serial transmission on downstream channel – Serial output clock frequency: – Fractional clock divider for precise frequency control ...
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MultiCAN Controller The MultiCAN module provides two independent CAN nodes, representing two serial communication interfaces. The number of available message objects 64. f CAN Clock f Control CLC Message Object Buffer Address Decoder Objects Interrupt Control Figure 2-8 Overview ...
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Features • Compliant with ISO 11898 • CAN functionality according to CAN specification V2.0 B active • Dedicated control registers for each CAN node • Data transfer rates Mbit/s • Flexible and powerful message transfer control and ...
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interrupt output lines are available. Interrupt requests can be routed individually to one of the 16 interrupt output lines. – Message post-processing notifications can be combined flexibly into a dedicated register field of 256 notification bits. ...
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Micro Link Interface This TC1736 contains one Micro Link Interface, MLI0. The Micro Link Interface (MLI fast synchronous serial interface to exchange data between microcontrollers or other devices, such as stand-alone peripheral components. Figure 2-9 shows how ...
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Figure 2-10 shows a general block diagram of the MLI module. f Fract. SYS Divider TR[3:0] BRKOUT Move SR[7:0] Engine Figure 2-10 General Block Diagram of the MLI Modules The MLI transmitter and MLI receiver communicate with other MLI receivers ...
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General Purpose Timer Array (GPTAv5) The TC1736 contains the General Purpose Timer Array (GPTA0). global view of the GPTA module. The GPTA provides a set of timer, compare, and capture functionalities that can be flexibly combined to form signal ...
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Functionality of GPTA0 The General Purpose Timer Array (GPTA0) provides a set of hardware modules required for high-speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. • Phase Discrimination Logic units ...
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Mode, GPTA signal frequency in 3-sensor Mode • Duty Cycle Measurement (DCM) – Four independent units – 100% margin and time-out handling f – maximum resolution GPTA f – ...
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On-chip Trigger Unit • 16 on-chip trigger signals I/O Sharing Unit • Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface 2.5.7 Analog-to-Digital Converter (ADC0, ADC1) The analog to digital converter module (ADC) allows the ...
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Input multiplexer width of 16 possible analog input channels (not all of them are necessarily available on pins) V • and 1 alternative reference input at channel 0 AREF • Programmable sample time (in periods of • Wide range ...
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V f FADC Clock f Control CLC SRx Interrupt Control SRx DMA TS[H:A] GS[H:A] Figure 2-13 Block Diagram of the FADC Module with 2 Input Channels Data Sheet Intro, V1 DDAF FAREF DDMF FAGND SSAF ...
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As shown in Figure 2-13, the main FADC functional blocks are: • An Input Structure containing the differential inputs and impedance control. • An A/D Converter Stage responsible for the analog-to-digital conversion including an input multiplexer to select between the ...
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Analog Input Stages FAIN2P Rp FAIN2N Rn Rp FAIN3P FAIN3N Rn V DDIF Figure 2-14 FADC Input Structure in TC1736 Data Sheet Intro, V1.1 Channel Amplifier Stages V DDMF V SSMF V DDMF V SSMF V SSMF 50 TC1736 Introduction ...
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On-Chip Debug Support (OCDS) The TC1736 contains resources for different kinds of “debugging”, covering needs from software development to real-time-tuning. These resources are either embedded in specific modules (e.g. breakpoint logic of the TriCore) or part of a central ...
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Calibration Support Two main use cases are catered for by resources in addition the OCDS Level 1 infrastructure: Overlay of non-volatile on-chip memory and non-intrusive signaling: • SRAM for Overlay. • Can be split into up to ...
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Self-Test Support Some manufacturing tests can be invoked by the application (e.g. after power-on) if needed: • Hardware-accelerated checksum calculation (e.g. for Flash content). 2.6.6 FAR Support To efficiently locate and identify faults after integration of a TC1736 into ...
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Pinning 3.1 TC1736 Pinning Figure 3-1 shows the TC1736 logic symbol. 3.1.1 Logic Symbol PORST TESTMODE General Control TCK/DAP0 TDI/BRKIN/ OCDS / BRKOUT JTAG Control TDO/DAP2/ BRKOUT TMS / DAP1 Analog Inputs Analog Power Supply Digital Circuitry Power Supply ...
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Pin Configuration Figure 3-2 shows the pin configuration of the TC1736 package PG-LQFP-144-10. 1 OUT40/IN40/P5.0 2 OUT41/IN41/P5.1 3 OUT42/IN42/P5.2 4 OUT43/IN43/P5.3 5 OUT80/P9.0 6 OUT81/P9.1 7 OUT44/IN44/P5.4 8 OUT45/IN45/P5.5 9 OUT46/IN46/P5.6 10 OUT47/IN47/P5.7 TCLK0/P5. ...
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Pin Definitions and Functions Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. Port 0 121 P0.0 I/O0 IN0 I HWCFG0 I OUT0 O1 OUT56 O2 Reserved O3 122 P0.1 I/O0 IN1 I HWCFG1 I OUT1 O1 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 134 P0.4 I/O0 IN4 I HWCFG4 I OUT4 O1 OUT60 O2 Reserved O3 135 P0.5 I/O0 IN5 I HWCFG5 I OUT5 O1 OUT61 O2 Reserved O3 141 P0.6 I/O0 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 136 P0.12 I/O0 IN12 I OUT12 O1 OUT68 O2 Reserved O3 137 P0.13 I/O0 IN13 I OUT13 O1 OUT69 O2 Reserved O3 143 P0.14 I/O0 IN14 I REQ4 I ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 95 P1.1 I/O0 IN17 I OUT17 O1 OUT73 O2 Reserved O3 86 P1.4 I/O0 IN20 I EMGSTOP I OUT20 O1 OUT76 O2 Reserved O3 74 P1.8 I/O0 IN24 I ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 76 P1.10 I/O0 IN26 I IN50 I OUT26 O1 OUT50 O2 SLSO17 O3 77 P1.11 I/O0 IN27 I IN51 I SCLK1B I OUT27 O1 OUT51 O2 SCLK1B O3 93 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 62 P2.1 I/O0 IN33 I TREADY0A I OUT33 O1 SLSO03 O2 SLSO13 O3 63 P2.2 I/O0 IN34 I OUT34 O1 TVALID0 O2 Reserved O3 64 P2.3 I/O0 IN35 I ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 67 P2.6 I/O0 IN38 I RVALID0A I OUT38 O1 OUT38 O2 Reserved O3 68 P2.7 I/O0 IN39 I RDATA0A I OUT39 O1 OUT39 O2 Reserved O3 132 P2.8 I/O0 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 131 P2.12 I/O0 MTSR1A I MTSR1A O1 Reserved O2 SOP0B O3 133 P2.13 I/O0 SLSI11 I SDI0 I Reserved O1 Reserved O2 Reserved O3 Port 3 112 P3.0 I/O0 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 106 P3.3 I/O0 MRST0 I MRST0 O1 MRST0 O2 OUT87 O3 108 P3.4 I/O0 MTSR0 I MTSR0 O1 MTSR0 O2 OUT88 O3 102 P3.5 I/O0 SLSO00 O1 SLSO10 O2 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 114 P3.9 I/O0 RXD1A I RXD1A O1 RXD1A O2 OUT91 O3 113 P3.10 I/O0 REQ0 I Reserved O1 Reserved O2 OUT92 O3 120 P3.11 I/O0 REQ1 I Reserved O1 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 110 P3.14 I/O0 RXDCAN1 I RXD1B I RXD1B O1 RXD1B O2 OUT96 O3 109 P3.15 I/O0 TXDCAN1 O1 TXD1 O2 OUT97 O3 Port 4 72 P4.2 I/O0 IN30 I ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. Port 5 1 P5.0 I/O0 IN40 I OUT40 O1 Reserved O2 Reserved O3 2 P5.1 I/O0 IN41 I OUT41 O1 Reserved O2 Reserved O3 3 P5.2 I/O0 IN42 I ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 8 P5.5 I/O0 IN45 I OUT45 O1 Reserved O2 Reserved O3 9 P5.6 I/O0 IN46 I OUT46 O1 Reserved O2 Reserved O3 10 P5.7 I/O0 IN47 I OUT47 O1 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 18 P5.11 I/O0 RCLK0B I Reserved O1 Reserved O2 Reserved O3 19 P5.12 I/O0 TDATA0 O1 SLSO07 O2 Reserved O3 20 P5.13 I/O0 TVALID0B O1 SLSO16 O2 Reserved O3 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl. 6 P9.1 I/O0 Reserved O1 OUT81 O2 Reserved O3 Analog Input Port 57 AN0 I 56 AN1 I 55 AN2 I 54 AN3 I 53 AN4 I 52 AN5 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl – SSM V 42 – AREF0 41 V – AGND0 V 26 – DDMF V 25 – DDAF 27 V – SSMF V – SSAF V 28 ...
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Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package) Pin Symbol Ctrl – DDOSC3 V 83 – SSOSC 117 V – DDFL3 81 XTAL1 I 82 XTAL2 O 87 TDI/BRKIN/ I/O BRKOUT 88 TMS/DAP1 I/O 89 TDO/DAP2/ I/O BRKIN/ ...
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O = Output O0 = Output with IOCR bit field selection PCx = 1X00 O1 = Output with IOCR bit field selection PCx = 1X01 O2 = Output with IOCR bit field selection PCx = 1X10 O3 = Output with ...
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Identification Registers The Identification Registers uniquely identify a module or the whole device. Table 4-1 TC1736 Identification Registers Short Name Value ADC0_ID 0058 C000 ADC1_ID 0058 C000 ASC0_ID 0000 4402 ASC1_ID 0000 4402 CAN_ID 002B C061 CBS_JDPID 0000 6350 ...
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Table 4-1 TC1736 Identification Registers (cont’d) Short Name Value SSC0_ID 0000 4511 SSC1_ID 0000 4511 STM_ID 0000 C006 Data Sheet Address F010 0108 H H F010 0208 H H F000 0208 TC1736 Identification Registers Stepping – – ...
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Electrical Parameters 5.1 General Parameters 5.1.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1736 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a ...
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Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Table 2 Pad Driver and Pad Classes Overview Class ...
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Absolute Maximum Ratings Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated ...
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Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1736. All parameters specified in the following table refer to these operating conditions, unless otherwise noted. Table 4 Operating Condition Parameters ...
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Table 4 Operating Condition Parameters Parameter Absolute sum of short circuit currents of a pin group (see Table 5) Inactive device pin current Absolute sum of short circuit currents of the device External load capacitance 1) Digital supply voltages applied ...
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Table 5 Pin Groups for Overload/Short-Circuit Current Sum Parameter Group Pins 1 P5.[14:8] 2 P2.[7:0] 3 P4.[3:2]; P1.[11:8] 4 P1.4; TDI/BRKIN/BRKOUT; TMS/DAP1; TDO/DAP2/BRKIN/BRKOUT; TRST, TCK/DAP0; P1.[1:0]; P1.15; TESTMODE; ESR0; PORST; ESR1 5 P3.[10:0]; P3.[15:14] 6 P3.[13:11]; P0.[3:0] 7 P2.[13:8]; P0.[5:4]; ...
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DC Parameters 5.2.1 Input/Output Pins Table 6 Input/Output DC-Characteristics (Operating Conditions apply) Parameter Symbol General Parameters 1) Pull-up current | I | PUH I Pull-down | | PDL 1) current 1) C Pin capacitance IO (Digital I/O) Input only ...
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Table 6 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol t Spike filter pass- SF2 through pulse duration V Class A Pads ( = 3. 3.3V ± 5%) DDP V Output low voltage OLA 2)3) V Output ...
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Table 6 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol I Input leakage OZA1 current Class A1 pins Class D Pads See ADC Characteristics 1) Not subject to production test, verified by design / characterization. 2) Only one of these parameters ...
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Analog to Digital Converters (ADC0/ADC1) All ADC parameters are optimized for and valid in the range of Table 7 ADC Characteristics (Operating Conditions apply) Parameter Symbol Analog supply V DDM voltage Analog ground SSM voltage V ...
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Table 7 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol 9)5) EA Offset error OFF I Input leakage CC OZ1 current at analog inputs of ADC0/1 11) 12) 13) Input leakage I OZ2 current AREF0/1 per module ...
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Table 7 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol C Switched AINSW capacitance at the analog voltage inputs R ON resistance of AIN the transmission gates in the analog voltage path R ON resistance AIN7T for the ADC test ...
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Only one of these parameters is tested, the other is verified by design characterization. 13) The leakage current decreases typically 30% for junction temperature decrease of 10 14) Applies to AINx, when used as auxiliary reference inputs. 15) I ...
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Table 8 Conversion Time (Operating Conditions apply) Parameter Symbol CC 2 × t Conversion C time with post-calibration Conversion time without post-calibration R EXT AIN EXT V AREF Figure 2 ADC0/ADC1 Input Circuits ...
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Fast Analog to Digital Converter (FADC) All parameters apply to FADC used in differential mode, which is the default and the intended mode of operation, and which takes advantage of many error cancelation effects inherent to differential measurements in ...
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Table 9 FADC Characteristics (Operating Conditions apply) (cont’d) Parameter Symbol t Conversion time C_FADC Converter clock f FADC R Input resistance of FAIN the analog voltage path (Rn, Rp) Channel amplifier f COFF 9) cutoff frequency Settling time of a ...
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FAINxN V FAGND FAINxP V V FAREF V Figure 4 FADC Input Circuits Data Sheet FADC Analog Input Stage FAREF R P FADC Reference Voltage Input Circuitry FAREF I FAREF FAGND 92 Electrical Parameters - + /2 ...
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Oscillator Pins Table 10 Oscillator Pins Characteristics (Operating Conditions apply) Parameter Symbol f Frequency range OSC V Input low voltage at ILX 1) XTAL1 Input high voltage at V IHX 1) XTAL1 I Input current at IX1 XTAL1 1) ...
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The following formula calculates the temperature measured by the DTS in [ RESULT bitfield of the DTSSTAT register. Data Sheet DTSSTAT RESULT Tj = ----------------------------------------------------------------- - TC1736 Electrical Parameters o C] from the 619 – V1.1, ...
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Power Supply Current The default test conditions (differences explicitly specified) are 1. 3. DDP Table 12 Power Supply Currents, Maximum Power Consumption Parameter Symbol I Core active mode 1) 2) supply current ...
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Not tested in production separately, verified by design / characterization. 5) This value assumes worst case of reading flash line with all cells erased. In case of 50% cells written with “1” and 50% cells written with “0”, the ...
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AC Parameters All AC parameters are defined with the temperature compensation disabled. That means, keeping the pads constantly at maximum strength. 5.3.1 Testing Waveforms 90% 10 Figure 5 Rise/Fall Time Parameters V D ...
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Output Rise/Fall Times Table 13 Output Rise/Fall Times (Operating Conditions apply) Parameter Symbol Class A1 Pads Rise/fall times , RA1 FA1 Class A2 Pads t t Rise/fall times , RA2 FA2 1) 1) Not all parameters ...
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Power Sequencing V 5V 3.3V 1.5V V DDP Figure 3 1.5 V Power-Up/Down Sequence The following list of rules applies to the power-up/down sequence: V • All ground pins must be externally connected ...
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The PORST signal may be deactivated after all supplies and the oscillator have reached stable operation, within the normal operating conditions normal power down the PORST signal should be activated within the normal operating range, and then ...
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Power, Pad and Reset Timing Table 14 Power, Pad and Reset Timing Parameters Parameter V Min. voltage to DDP ensure defined pad 1) states 2) Oscillator start-up time Minimum PORST active time after power supplies are stable at operating ...
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OSCS 0,3 × This parameter is verified by device characterization. The external oscillator circuitry must be DDOSC3 optimized by the customer and checked for negative resistance as recommended and specified ...
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Phase Locked Loop (PLL) Note: All PLL characteristics defined on this and the next page are not subject to production test, but verified by design characterization. Table 15 PLL Parameters (Operating Conditions apply) Parameter Accumulated jitter VCO frequency range ...
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With rising number of clock cycles the maximum jitter increases linearly value m of that is defined by the K2-factor of the PLL. Beyond this value of accumulated jitter remains at a constant value. Further, a ...
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These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet Electrical Parameters 105 TC1736 V1.1, 2009-08 ...
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JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table ...
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V 0 Figure 11 Test Clock Timing (TCK) TCK TMS TDI t 9 TDO Figure 12 JTAG Timing Data Sheet ...
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DAP Interface Timing The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 17 DAP Interface Timing Parameters (Operating Conditions apply) ...
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DAP0 DAP1 Figure 14 DAP Timing Host to Device DAP1 Figure 15 DAP Timing Device to Host Data Sheet Electrical Parameters 109 TC1736 MC_ DAP1_RX MC_ DAP1_TX V1.1, ...
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Peripheral Timings Note: Peripheral timing parameters are not subject to production test. They are verified by design / characterization. 5.3.8.1 Micro Link Interface (MLI) Timing MLI Transmitter Timing TCLKx TDATAx TVALIDx TREADYx MLI Receiver Timing RCLKx RDATAx RVALIDx RREADYx ...
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Table 18 MLI Transmitter/Receiver Timing (Operating Conditions apply), C Parameter MLI Transmitter Timing TCLK clock period TCLK high time TCLK low time TCLK rise time TCLK fall time TDATA/TVALID output delay time TREADY setup time to TCLK rising edge TREADY ...
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The RCLK max. input rise/fall times are best case parameters for input signal rise/fall times can be used for longer RCLK clock periods. 5.3.8.2 Micro Second Channel (MSC) Interface Timing Table 19 MSC Interface Timing (Operating Conditions apply), C ...
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SSC Master / Slave Mode Timing Table 20 SSC Master/Slave Mode Timing (Operating Conditions apply), C Parameter Master Mode Timing SCLK clock period MTSR/SLSOx delay from SCLK rising edge MRST setup to SCLK falling edge MRST hold from SCLK ...
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SCLK 1) MTSR 1) MRST 2) SLSOx 1) This timing is based on the following setup: CON.PH = CON. The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK ...
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Package and Reliability 5.4.1 Package Parameters Table 21 Thermal Parameters (Operating Conditions apply) Device Package TC1736 PG-LQFP-144-10 1) The top and bottom thermal resistances between the case and the ambient ( with the thermal resistances between the junction and ...
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Package Outline 0.5 17.5 2) 0.22 ±0.05 0.08 A 144 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of ...
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Flash Memory Parameters The data retention time of the TC1736’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 22 ...
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Quality Declarations Table 23 Quality Parameters Parameter Symbol Operation Lifetime ESD susceptibility V HBM according to Human Body Model (HBM) V ESD susceptibility CDM according to Charged Device Model (CDM) Moisture MSL Sensitivity Level 1) This ...
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... Published by Infineon Technologies AG ...