UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 642

• Manufacturer Part Number: UPD70F3747GB-GAH-AX
• Description: MCU 32BIT V850ES/HX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Hx3r

Specifications of UPD70F3747GB-GAH-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.6.5 Data consistency check function
bitwise when data including a Sync Break Field, Sync Field, Identifier Field, and Check SUM Field is transmitted. If a
mismatch is detected and if reception is completed before transmission is completed to correct a mismatch between
the transmit data and receive data due to an error between the transmission and reception operations, the status
interrupt request signal (INTUDnS) is output and the data consistency error flag (UDnDCE) is set at the end of the
frame.
transmit data register (UDnTX) (the written data in UDnTX is ignored). Even if the SBF transmission trigger bit
(UDnSTT) is set, SBTT is cleared and SBF is not transmitted. To resume transmission, clear the data consistency
error flag (UDnDCE) and then write transmit data to the transmit data register (UDnTX) or set the SBF transmission
trigger bit (UDnSTT).
if the stop bit length is specified by the stop bit length select bit (UDnSL) to be 2 bits, consistency of the second stop
bit is not checked.
executed, however, consistency between transmit data and input data pin level is checked even if the reception enable
bit is disabled (UDnRXE = 0). When UDnRXE = 0, reception itself is not executed. Consequently, the reception
complete interrupt request signal (INTUDnR) is not generated when receive data is stored, nor is the status interrupt
request signal (INTUDnS) generated when UDnSSF, UDnFE, or UDnOVE is set. It is therefore not necessary to read
receive data.
640
When the data consistency check select bit (UDnDCS) is set to “1”, transmit data and receive data are compared
In addition, the next transmission is not executed even if the next transmit data has already been written to the
Consistency of data is checked from the start bit of transmission to the first stop bit during SBF transmission. Even
When only reception is executed (without transmission), data is not checked for consistency. When transmission is
A data consistency error is detected in the following cases.
• If a mismatch between transmit data and receive data is detected during transmission (from the start bit to the
• If reception is completed before transmission is completed when UDnSRF = 0
• If the rising edge of input data is detected during SBF transmission when UDnSRF = 1 and UDnSRS = 0
• If “1” is detected in the input data during SBF transmission when UDnSRF = 1 and UDnSRS = 1
• If “0” is detected in the input data when the first stop bit is transmitted
Note Except when UDnRXE = 0
Cautions 1. If data consistency check select bit UDnDCS = 0, the data consistency error flag (UDnDCE) is
first stop bit)
2. Occurrence of a data consistency error does not affect the operation to store receive data in
3. If SBF is transmitted when UDnSRS = 0, UDnDCS = 1, and UDnSRF = 0, reception ends at the
fixed to “0”.
the UDnRX register. However, the data is stored in the register if there is a possibility of a
framing error.
position of the stop bit (10th bit) of data (reception ends before transmission ends).
Consequently, a consistency error occurs even if the transmit data and receive data do not
mismatch.
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE D (UARTD)
User’s Manual U18854EJ2V0UD
Note