UPD78F1144AGK-GAJ-AX Renesas Electronics America, UPD78F1144AGK-GAJ-AX Datasheet - Page 701
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UPD78F1144AGK-GAJ-AX
Manufacturer Part Number
UPD78F1144AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1144AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Instruction
Increment/
decrement
Shift
Group
2.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
3. cnt indicates the bit shift count.
Mnemonic
INC
DEC
INCW
DECW
SHR
SHRW
SHL
SHLW
SAR
SARW
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
When the program memory area is accessed.
register (CKC).
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum.
r
saddr
!addr16
[HL+byte]
ES:!addr16
ES: [HL+byte]
r
saddr
!addr16
[HL+byte]
ES:!addr16
ES: [HL+byte]
rp
saddrp
!addr16
[HL+byte]
ES:!addr16
ES: [HL+byte]
rp
saddrp
!addr16
[HL+byte]
ES:!addr16
ES: [HL+byte]
A, cnt
AX, cnt
A, cnt
B, cnt
C, cnt
AX, cnt
BC, cnt
A, cnt
AX, cnt
Operands
Table 26-5. Operation List (12/17)
CHAPTER 26 INSTRUCTION SET
Bytes
1
2
3
3
4
4
1
2
3
3
4
4
1
2
3
3
4
4
1
2
3
3
4
4
2
2
2
2
2
2
2
2
2
User’s Manual U17854EJ9V0UD
Note 1 Note 2
1
2
2
2
3
3
1
2
2
2
3
3
1
2
2
2
3
3
1
2
2
2
3
3
1
1
1
1
1
1
1
1
1
Clocks
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
r ← r + 1
(saddr) ← (saddr) + 1
(addr16) ← (addr16) + 1
(HL+byte) ← (HL+byte) + 1
(ES, addr16) ← (ES, addr16) + 1
((ES:HL) + byte) ← ((ES:HL) + byte) + 1
r ← r − 1
(saddr) ← (saddr) − 1
(addr16) ← (addr16) − 1
(HL+byte) ← (HL+byte) − 1
(ES, addr16) ← (ES, addr16) − 1
((ES:HL) + byte) ← ((ES:HL) + byte) − 1
rp ← rp + 1
(saddrp) ← (saddrp) + 1
(addr16) ← (addr16) + 1
(HL+byte) ← (HL+byte) + 1
(ES, addr16) ← (ES, addr16) + 1
((ES:HL) + byte) ← ((ES:HL) + byte) + 1
rp ← rp − 1
(saddrp) ← (saddrp) − 1
(addr16) ← (addr16) − 1
(HL+byte) ← (HL+byte) − 1
(ES, addr16) ← (ES, addr16) − 1
((ES:HL) + byte) ← ((ES:HL) + byte) − 1
(CY ← A
(CY ← AX
(CY ← A
(CY ← B
(CY ← C
(CY ← AX
(CY ← BC
(CY ← A
(CY ← AX
CLK
0
7
7
0
7
, A
, A
, B
, A
0
, C
0
15
, AX
15
) selected by the system clock control
, AX
, AX
, BC
m−1
m
m
m−1
m
← A
← B
m−1
← C
m−1
← A
← A
m
m
Operation
← AX
← AX
← BC
m−1
m−1
← AX
m−1
m
m
,
, A
, B
, A
, C
A
m
7
m−1
, AX
0
0
7
m−1
0
m
← 0) × cnt
← 0) × cnt
← 0) × cnt
← A
, AX
← 0) × cnt
, AX
, BC
15
7
← AX
15
) × cnt
0
0
← 0) × cnt
← 0) × cnt
← 0) × cnt
15
) × cnt
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
699
×
×
×
×
×
×
×
×
×
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