UPD78F1144AGK-GAJ-AX Renesas Electronics America, UPD78F1144AGK-GAJ-AX Datasheet - Page 613
UPD78F1144AGK-GAJ-AX
Manufacturer Part Number
UPD78F1144AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1144AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 613 of 880
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(2) STOP mode release
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
Figure 17-5. Operation Timing When STOP Mode Is Released (Release by Unmasked Interrupt Request)
Notes 1. When the oscillation stabilization time set by OSTS is equal to or shorter than 61
Remark f
The STOP mode can be released by the following two sources.
2. The wait time is as follows:
is retained to a maximum of "61
f
f
EX
IH
CLK
:
:
: CPU/peripheral hardware clock frequency
STOP mode
• When vectored interrupt servicing is carried out:
• When vectored interrupt servicing is not carried out:
Internal high-speed oscillation clock frequency
External main system clock frequency
STOP mode release
Wait for oscillation accuracy stabilization
(oscillation stabilization time set by OSTS)
CHAPTER 17 STANDBY FUNCTION
Supply of the CPU clock is stopped (when f
Supply of the CPU clock is stopped (when f
HALT status
User’s Manual U17854EJ9V0UD
μ
s + wait time."
Internal high-speed
Wait
Wait
oscillation clock
Note 2
Note 2
Note 1
Clock switched by software
Clock switched by software
10 to 12 clocks
5 or 6 clocks
High-speed system clock
High-speed system clock
CLK
CLK
= f
= f
EX
IH
: 23 to 61 s)
: 23 to 61 s)
High-speed system clock
μ
μ
μ
s, the HALT status
611
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