UPD78F1144AGK-GAJ-AX Renesas Electronics America, UPD78F1144AGK-GAJ-AX Datasheet - Page 442
UPD78F1144AGK-GAJ-AX
Manufacturer Part Number
UPD78F1144AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1144AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.6.4 LIN reception
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
440
Remark f
Support of LIN communication
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
Of UART reception, UART3 supports LIN communication.
For LIN reception, channel 3 of unit 1 (SAU1) is used.
Figure 11-87 outlines a reception operation of LIN.
specifications (see CHAPTER 27
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
f
MCK
CLK
UART
: System clock frequency
: Operation clock (MCK) frequency of target channel
Not supported
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
• Framing error detection flag (FEF13)
• Parity error detection flag (PEF13)
• Overrun error detection flag (OVF13)
8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity check
• Appending odd parity check
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
MCK
/6 [bps] (SDR13 [15:9] = 2 or more), Min. f
CHAPTER 11 SERIAL ARRAY UNIT
UART0
−
−
−
−
User’s Manual U17854EJ9V0UD
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
Not supported
UART1
−
−
−
−
CLK
/(2 × 2
11
× 128) [bps]
Supported
Channel 0 of SAU1
RxD3
INTSR3
INTSRE3
Note
UART3
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