UPD78F1144AGK-GAJ-AX Renesas Electronics America, UPD78F1144AGK-GAJ-AX Datasheet - Page 630
UPD78F1144AGK-GAJ-AX
Manufacturer Part Number
UPD78F1144AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
UPD78F1144AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19.4 Cautions for Power-on-Clear Circuit
voltage (V
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
628
Note 1
In a system where the supply voltage (V
<Action>
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Notes 1.
Remark n: Channel number (n = 0 to 7)
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
POC
2.
), the system may be repeatedly reset and released from the reset status. In this case, the time from
If reset is generated again during this period, initialization processing <2> is not started.
A flowchart is shown on the next page.
No
Figure 19-3. Example of Software Processing After Reset Release (1/2)
Setting timer array unit
(to measure 50 ms)
50 ms has passed?
processing <1>
processing <2>
(TMIF0n = 1?)
Clearing WDT
Initialization
Initialization
Reset
Yes
Power-on-clear
CHAPTER 19 POWER-ON-CLEAR CIRCUIT
DD
User’s Manual U17854EJ9V0UD
) fluctuates for a certain period in the vicinity of the POC detection
;
; f
; Initial setting for port.
Check the reset source, etc.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Source: f
Timer starts (TS0n = 1).
CLK
= Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default)
where comparison value = 102: ≅ 50 ms
CLK
(8.4 MHz (MAX.))/2
Note 2
12
,
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