UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 956

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
A/D
converter
Function
ADCRH: 8-bit A/D
conversion
register
ADS: Analog input
channel
specification
register
ADS: Analog input
channel
specification
register,
ADPC: A/D port
configuration
register (ADPC)
ADPC: A/D port
configuration
register (ADPC)
Port mode
register 2 (PM2)
Basic operations
of A/D converter
A/D conversion
operation
Operating current
in STOP mode
Input range of
ANI0 to ANI7
Conflicting
operations
Details of
Function
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents
of ADCRH may become undefined. Read the conversion result following conversion
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
If data is read from ADCRH, a wait cycle is generated. Do not read data from
ADCRH when the peripheral hardware clock (f
CHAPTER 36 CAUTIONS FOR WAIT.
Be sure to clear bits 3 to 7 to “0”.
If data is written to ADS, a wait cycle is generated. Do not write data to ADS when
the peripheral hardware clock (f
CAUTIONS FOR WAIT.
Set a channel to be used for A/D conversion in the input mode by using port mode
register 2 (PM2).
If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when
the peripheral hardware clock (f
CAUTIONS FOR WAIT.
For the 38-pin products of 78K0/KC2, be sure to set bits 6 and 7 of PM2 to “1”, and
bits 6 and 7 of P2 to “0”.
Make sure the period of <1> to <5> is 1
Make sure the period of <1> to <5> is 1
<1> may be done between <2> and <4>.
<1> can be omitted. However, ignore data of the first conversion after <5> in this
case.
The period from <6> to <9> differs from the conversion time set using bits 5 to 1
(FR2 to FR0, LV1, LV0) of ADM. The period from <8> to <9> is the conversion time
set using FR2 to FR0, LV1, and LV0.
The A/D converter stops operating in the STOP mode. At this time, the operating
current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0. To restart from the standby status, clear bit 0
(ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation.
Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AV
higher and AV
an analog input channel, the converted value of that channel becomes undefined. In
addition, the converted values of the other channels may also be affected.
If conflict occurs between A/D conversion result register (ADCR, ADCRH) write and
ADCR or ADCRH read by instruction upon the end of conversion, ADCR or ADCRH
read has priority. After the read operation, the new conversion result is written to
ADCR or ADCRH.
If conflict occurs between ADCR or ADCRH write and A/D converter mode register
(ADM) write, analog input channel specification register (ADS), or A/D port
configuration register (ADPC) write upon the end of conversion, ADM, ADS, or ADPC
write has priority. ADCR or ADCRH write is not performed, nor is the conversion end
interrupt signal (INTAD) generated.
SS
or lower (even in the range of absolute maximum ratings) is input to
PRS
PRS
) is stopped. For details, see CHAPTER 36
) is stopped. For details, see CHAPTER 36
Cautions
μ
μ
s or more.
s or more.
PRS
) is stopped. For details, see
APPENDIX D LIST OF CAUTIONS
REF
or
p. 417
p. 417
p. 418
p. 418
pp. 418,
419
p. 419
p. 420
p. 421
p. 425
p. 425
p. 425
p. 425
p. 428
p. 428
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