UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 545

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(4) Synchronization control
Busy control and strobe control are functions used to synchronize transmission/reception between the master
device and a slave device.
By using these functions, a shift in bits being transmitted or received can be detected.
(a) Busy control option
Caution Busy control cannot be used simultaneously with the interval time control function of
Busy control is a function to keep the serial transmission/reception by the master device waiting while the
busy signal output by a slave device to the master is active.
When using this busy control option, the following conditions must be satisfied.
• Bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1.
• Bit 4 (BUSYE0) of serial status register 0 (CSIS0) is set to 1.
Figure 17-23 shows the system configuration of the master device and slave device when the busy control
option is used.
The master device inputs the busy signal output by the slave device to the BUSY0/BUZ/INTP7/P141 pin. The
master device samples the input busy signal in synchronization with the falling of the serial clock. Even if the
busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the
master is not kept waiting. If the busy signal is active at the rising edge of the serial clock one clock after
completion of transmission/reception of the 8-bit data, the busy input becomes valid. After that, the master
transmission/reception is kept waiting while the busy signal is active.
The active level of the busy signal is set by bit 3 (BUSYLV0) of CSIS0.
BUSYLV0 = 1: Active-high
BUSYLV0 = 0: Active-low
When using the busy control option, select the master mode.
implemented in the slave mode.
Figure 17-24 shows the example of the operation timing when the busy control option is used.
Figure 17-23. System Configuration When Busy Control Option Is Used
automatic data transfer interval specification register 0 (ADTI0).
Master device
(78K0/KF2)
SCKA0
BUSY0
SOA0
SIA0
SCKA
SIA
SOA
Busy output
CHAPTER 17 SERIAL INTERFACE CSIA0
Slave device
Control with the busy signal cannot be
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