UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 946

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Port
function
Clock
generator
Function
P121/X1/OCD0A,
P122/X2/EXCLK/O
CD0B, P123/XT1,
P124/XT2/EXCLKS
Port mode
registers
Port register
(78K0/KC2)
ADPC: A/D port
configuration
register
1-bit manipulation
instruction for
port register n
(Pn)
OSCCTL: Clock
operation mode
select register
Details of
Function
When using the P121 to P124 pins to connect a resonator for the main system clock
(X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main
system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1
oscillation mode, or external clock input mode must be set by using the clock
operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation
mode select register (OSCCTL) and (3) Setting of operation mode for subsystem
clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are I/O
port pins). At this time, setting of the PM121 to PM124 and P121 to P124 pins is not
necessary.
Process the P121/X1/OCD0A pin of the products mounted with the on-chip debug
function (
connected to a flash memory programmer or an on-chip debug emulator (see the
table on p.197).
Be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM2, bits 4 to 7 of PM3, bits 2 to 7 of
PM6, bits 3 to 7 of PM12 to 1. (78K0/KB2)
For the 38-pin products, be sure to set bits 2 to 7 of PM0, bits 6 and 7 of PM2, bits 4
to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and bits 5 to 7
of PM12 to “1”. Also, be sure to set bits 0 and 1 of PM4, and bits 2 and 3 of PM7 to
“0”.
For the 44-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits 2
to 7 of PM4, bits 4 to 7 of PM6, bits 4 to 7 of PM7, and bits 5 to 7 of PM12 to “1”.
For the 48-pin products, be sure to set bits 2 to 7 of PM0, bits 4 to 7 of PM3, bits 2
to 7 of PM4, bits 4 to 7 of PM6, bits 6 and 7 of PM7, bits 5 to 7 of PM12, and bits 1
to 7 of PM14 to “1”. (78K0/KC2)
Be sure to set bits 4 to 7 of PM0, bits 4 to 7 of PM3, bits 2 to 7 of PM4, bits 4 to 7 of
PM6, bits 5 to 7 of PM12, and bits 1 to 7 of PM14 to 1. (78K0/KD2)
Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 4 to 7 of PM4, bits 4 to 7 of PM5,
bits 4 to 7 of PM6, bits 5 to 7 of PM12, and bits 2 to 7 of PM14 to “1”. (78K0/KE2)
Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 5 to 7 of PM12, and bits 6 and 7
of PM14 to “1”. (78K0/KF2)
For the 38-pin products, be sure to set bits 6 and 7 of P2, bits 0 and 1 of P4, and
bits 2 and 3 of P7 to “0”.
Set the channel used for A/D conversion to the input mode by using port mode
register 2 (PM2).
If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC
when the peripheral hardware clock is stopped. For details, see CHAPTER 36
CAUTIONS FOR WAIT.
When a 1-bit manipulation instruction is executed on a port that provides both input
and output functions, the output latch value of an input port that is not subject to
manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from
input mode to output mode.
Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
exceeds 10 MHz.
Set AMPH before setting the main clock mode register (MCM).
μ
PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is
Cautions
APPENDIX D LIST OF CAUTIONS
p. 196
p. 197
p. 205
p. 206
p. 207
p. 208
p. 209
p. 211
p. 220
p. 220
p. 224
pp. 230,
231
pp. 230,
231
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