UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 739

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
27.2 Operation List
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
8-bit data
transfer
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
3.
MOV
XCH
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
register (PCC).
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
Note 3
Note 3
Note 3
Bytes
2
3
3
1
1
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
1
1
1
1
2
2
3
1
1
2
2
2
Note 1
4
6
−
2
2
4
4
−
−
8
8
−
−
−
4
4
4
4
8
8
6
6
6
6
2
4
−
8
4
4
8
8
8
Clocks
Note 2
10
10
10
10
−
7
7
−
−
5
5
5
5
9
9
7
5
5
5
5
5
5
9
9
7
7
7
7
−
6
6
6
6
(saddr) ← byte
(saddr) ← A
(addr16) ← A
r ← byte
sfr ← byte
A ← r
r ← A
A ← (saddr)
A ← sfr
sfr ← A
A ← (addr16)
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
(HL) ← A
A ← (HL + byte)
(HL + byte) ← A
A ← (HL + B)
(HL + B) ← A
A ← (HL + C)
(HL + C) ← A
A ↔ r
A ↔ (saddr)
A ↔ (sfr)
A ↔ (addr16)
A ↔ (DE)
A ↔ (HL)
A ↔ (HL + byte)
A ↔ (HL + B)
A ↔ (HL + C)
CPU
) selected by the processor clock control
CHAPTER 27 INSTRUCTION SET
Operation
Z AC CY
×
×
Flag
×
×
×
×
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