UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 530

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
15.5.12 Arbitration
bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data
differs. This kind of operation is called arbitration.
(IICAS0) is set (1) via the timing by which the arbitration loss occurred, and the SCLA0 and SDAA0 lines are both set to
high impedance, which releases the bus.
condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
control.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
When several master devices simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in the IICA status register 0
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop
For details of interrupt request timing, refer to 15.5.8 Interrupt request (INTIICA0) generation timing and wait
Remark
Transfer lines
Master 1
Master 2
SDAA0
SDAA0
SDAA0
SCLA0
SCLA0
SCLA0
STD0: Bit 1 of IICA status register 0 (IICAS0)
STT0: Bit 1 of IICA control register 0 (IICACTL0)
Figure 15-22. Arbitration Timing Example
CHAPTER 15 SERIAL INTERFACE IICA
Master 1 loses arbitration
Hi-Z
Hi-Z
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