UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 436

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
12.4 A/D Converter Operations
12.4.1 Basic operations of A/D converter
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
<1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D
<2> Set bit 0 (ADCE) of ADM0 to 1 to start the operation of the A/D voltage comparator.
<3> Set channels for A/D conversion to analog I/O by using the A/D port configuration registers 0, 1 (ADPC0, ADPC1)
<4> Set the PGA operation to set the PGA output or the single AMP operation to set the operational amplifier output
<5> Select one channel for A/D conversion by using the analog input channel specification register (ADS).
<6> Start the conversion operation by setting bit 7 (ADCS) of ADM0 to 1.
<7> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<8> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
<9> Bit 9 of the successive approximation register (SAR) is set. The comparison voltage generator outputs (1/2)
<10> The voltage difference between the output voltage of the comparison voltage generator and sampled voltage is
<11> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The output
<12> Comparison is continued in this way up to bit 0 of SAR.
<13> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
<14> Repeat steps <7> to <13>, until ADCS is cleared to 0.
converter mode register 0 (ADM0).
and set to input mode by using port mode registers 1, 2 (PM1, PM2).
for analog input. (refer to CHAPTER 13 OPERATIONAL AMPLIFIERS).
(<7> to <14> are operations performed by hardware.)
sampled voltage is held until the A/D conversion operation has ended.
AV
compared by the voltage comparator. If the analog input is greater than (1/2) AV
set to 1. If the analog input is smaller than (1/2) AV
voltage of the comparison voltage generator is selected according to the preset value of bit 9, as described
below.
• Bit 9 = 1: (3/4) AV
• Bit 9 = 0: (1/4) AV
The output voltage of the comparison voltage generator and sampled voltage are compared and bit 8 of SAR is
manipulated as follows.
• Analog input voltage ≥ Output voltage of comparison voltage generator: Bit 8 = 1
• Analog input voltage < Output voltage of comparison voltage generator: Bit 8 = 0
value is transferred to the A/D conversion result register (ADCR, ADCRH, ADCRL) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <6>. To start A/D conversion again when
ADCE = 0, set ADCE to 1, wait for 1
from <5>.
REF
voltage.
REF
REF
μ
s or longer, and start <6>. To change a channel of A/D conversion, start
REF
, the MSB is reset to 0.
CHAPTER 12 A/D CONVERTER
REF
, the MSB of SAR remains
422