UPD78F0555MA-FAA-AX Renesas Electronics America, UPD78F0555MA-FAA-AX Datasheet - Page 509

• Manufacturer Part Number: UPD78F0555MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0555MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
Note The signal of this bit is invalid while IICE0 is 0.
Cautions concerning set timing
• For master reception:
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
• Cannot be set to 1 at the same time as stop condition trigger (SPT0).
• Setting the STT0 bit to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT0 = 0)
• Cleared by setting the STT0 bit to 1 while
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
STT0
device
communication reservation is prohibited.
0
1
Note
2. IICRSV: Bit 0 of IICA flag register 0 (IICAF0)
Do not generate a start condition.
When bus is released (in standby state, when IICBSY = 0):
When a third party is communicating:
In the wait state (when master device):
Generates a restart condition after releasing the wait.
If this bit is set (1), a start condition is generated (startup as the master).
• When communication reservation function is enabled (IICRSV = 0)
• When communication reservation function is disabled (IICRSV = 1)
STCF:
Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (3/4)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
Even if this bit is set (1), the STT0 bit is cleared and the STT0 clear flag (STCF) is set (1). No start
condition is generated.
Bit 7 of IICA flag register 0 (IICAF0)
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when
ACKE0 has been cleared to 0 and slave has been notified of final reception.
during the wait period that follows output of the ninth clock.
Start condition trigger
Condition for setting (STT0 = 1)
• Set by instruction
CHAPTER 15 SERIAL INTERFACE IICA
495