UPD78F9201MA-CAC-A Renesas Electronics America, UPD78F9201MA-CAC-A Datasheet - Page 334

• Manufacturer Part Number: UPD78F9201MA-CAC-A
• Description: MCU 8BIT 2KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9201MA-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

332
Standby
function
Reset
function
Power-
on-clear
circuit
Low-
voltage
detector
Function
HALT mode
setting and
operating
statuses
STOP mode
setting and
operating
statuses
Timing of reset
by overflow of
watchdog timer
RESF: Reset
control flag
register
Functions of
power-on-clear
circuit
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage detect
register
LVIS: Low-
voltage
detection level
select register
When used as
reset
Details of
Function
−
Because an interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
clear, the standby mode is immediately cleared if set.
Because an interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately cleared if set. Thus, in the STOP mode,
the normal operation mode is restored after the STOP instruction is executed and
then the operation is stopped for 34
stabilizing the oscillation set by the oscillation stabilization time select register
(OSTS) has elapsed when crystal/ceramic oscillation is used).
For an external reset, input a low level for 2
During reset signal generation, the system clock and low-speed internal oscillation
clock stop oscillating.
When the RESET pin is used as an input-only port pin (P34), the 78K0S/KU1+ is
reset if a low level is input to the RESET pin after reset is released by the POC
circuit, the LVI circuit and the watchdog timer and before the option byte is
referenced again. The reset status is retained until a high level is input to the
RESET pin.
The LVI circuit is not reset by the internal reset signal of the LVI circuit.
The watchdog timer is also reset in the case of an internal reset of the watchdog
timer.
Do not read data by a 1-bit memory manipulation instruction.
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
Because the detection voltage (V
V, use a voltage in the range of 2.2 to 5.5 V.
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
and released from the reset status. In this case, the time from release of reset to
the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
To stop LVI, follow either of the procedures below.
Be sure to set bits 2 to 6 to 0.
Bits 4 to 7 must be set to 0.
If a value other than the above is written during LVI operation, the value becomes
undefined at the very moment it is written, and thus be sure to stop LVI (bit
7(LVION) = 0 on the LVIM register) before writing.
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
If supply voltage (V
reset signal is not generated.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
APPENDIX D LIST OF CAUTIONS
User’s Manual U18172EJ3V0UD
DD
) ≥ detection voltage (V
POC
μ
) of the POC circuit is in a range of 2.1 V ±0.1
Cautions
s (TYP.) (after an additional wait time for
POC
DD
) fluctuates for a certain period in the
), the system may be repeatedly reset
μ
LVI
s or more to the RESET pin.
) when LVIM is set to 1, an internal
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