UPD78F9201MA-CAC-A Renesas Electronics America, UPD78F9201MA-CAC-A Datasheet - Page 239

• Manufacturer Part Number: UPD78F9201MA-CAC-A
• Description: MCU 8BIT 2KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9201MA-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

16.8.2 Cautions on self programming function
16.8.3 Registers used for self-programming function
• No instructions can be executed while a self programming command is being executed. Therefore, clear and
• Interrupts that occur during self programming can be acknowledged after self programming mode ends. To avoid
• RAM is not used while a self programming command is being executed.
• If the supply voltage drops or the reset signal is input while the flash memory is being written or erased,
• The value of the blank data set during block erasure is FFH.
• Set the CPU clock so that it is 1 MHz or more during self programming.
• Execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming
• If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT
• Check FPRERR using a 1-bit memory manipulation instruction.
• The state of the pins in self programming mode is the same as that in HALT mode.
• Since the security function set via on-board/off-board programming is disabled in self programming mode, the
• Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register
• Clear the value of the FLCMD register to 00H immediately before setting self-programming mode and normal
The following registers are used for the self-programming function.
• Flash programming mode control register (FLPMC)
• Flash protect command register (PFCMD)
• Flash status register (PFS)
• Flash programming command register (FLCMD)
• Flash address pointers H and L (FLAPH and FLAPL)
• Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and FLAPLC)
• Flash write buffer register (FLW)
The 78K0S/KU1+ has an area called a protect byte at address 0081H of the flash memory.
(1) Flash programming mode control register (FLPMC)
restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self
programming. Refer to Table 16-10 for the time taken for the execution of self programming.
this operation, disable interrupt servicing (by setting MK0 to FFH, and executing the DI instruction) before a
mode is shifted from the normal mode to the self programming mode with a specific sequence.
writing/erasing is not guaranteed.
mode, then execute self programming. At this time, the HALT instruction is automatically released after 10
(MAX.) + 2 CPU clocks (f
instructions immediately after executing a specific sequence to set self-programming mode, wait for 8
releasing the HALT status, and then execute self programming.
self programming command can be executed regardless of the security function setting. To disable write or erase
processing during self programming, set the protect byte.
(FLAPHC) to 0 before executing the self programming command. If the value of these bits is 1 when executing
the self programming command, there is a possibility that device does not operate normally.
operation mode.
This register is used to set the operation mode when data is written to the flash memory in the self-
Data can be written to FLPMC only in a specific sequence (refer to 16.8.3 (2) Flash protect command
programming mode, and to read the set value of the protect byte.
register (PFCMD)) so that the application system does not stop by accident because of malfunction due to
noise or program hang-up.
CPU
).
CHAPTER 16 FLASH MEMORY
User’s Manual U18172EJ3V0UD
μ
s after
237
μ
s