DF2166VT33 Renesas Electronics America, DF2166VT33 Datasheet - Page 560

MCU FLASH 3V 512K 33MHZ 144TQFP

DF2166VT33

Manufacturer Part Number
DF2166VT33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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16.3.2
The bits 6 to 0 in HICR2 control interrupts from the LPC interface module to the slave processor
(this LSI). HICR3 and the bit 7 of HICR2 monitor the LPC interface pin states.
Bits 6 to 0 in HICR2 are initialized to H'00 by a reset or in hardware standby mode. The states of
the other bits are determined by the pin states.
The pin states can be monitored regardless of the LPC interface operating state or the operating
state of the functions that use pin multiplexing.
• HICR2
Rev. 3.00, 03/04, page 518 of 830
Bit
7
6
5
Bit Name Initial Value Slave Host Description
GA20
LRST
SDWN
Host Interface Control Registers 2 and 3 (HICR2, HICR3)
Undefined
0
0
R
R/(W)* 
R/(W)* 
R/W
GA20 Pin Monitor
LPC Reset Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
an LPC hardware reset occurs.
0: [Clearing condition]
1: [Setting condition]
LPC Shutdown Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
an LPC hardware shutdown request is generated.
0: [Clearing conditions]
1: [Setting condition]
Writing 0 after reading LRST = 1
LRESET pin falling edge detection
Writing 0 after reading SDWN = 1
LPC hardware reset
LPC software reset
LPCPD pin falling edge detection

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