DF2166VT33 Renesas Electronics America, DF2166VT33 Datasheet - Page 554

MCU FLASH 3V 512K 33MHZ 144TQFP

DF2166VT33

Manufacturer Part Number
DF2166VT33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2166VT33
Quantity:
9
Part Number:
DF2166VT33V
Manufacturer:
Exar
Quantity:
60
Part Number:
DF2166VT33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.3.1
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits
that determine pin output and the internal state of the LPC interface, and status flags that monitor
the internal state of the LPC interface.
HICR0 and HICR1 are initialized to H'00 by a reset or in hardware standby mode.
• HICR0
Rev. 3.00, 03/04, page 512 of 830
Bit
7
6
5
Bit Name Initial Value Slave Host Description
LPC3E
LPC2E
LPC1E
Host Interface Control Registers 0 and 1 (HICR0, HICR1)
0
0
0
R/W
R/W
R/W
R/W
LPC Enable 3 to 1
Enables or disables the LPC interface function.
When the host interface is enabled (at least one of
the three bits is set to 1), processing for data transfer
between the slave processor and the host processor
is performed using pins LAD3 to LAD0, LFRAME,
LRESET, LCLK, SERIRQ, CLKRUN, and LPCPD.
0: LPC channel 3 operation is disabled
1: LPC channel 3 operation is enabled
0: LPC channel 2 operation is disabled
1: LPC channel 2 operation is enabled
0: LPC channel 1 operation is disabled
1: LPC channel 1 operation is enabled
No address (LADR3) matches for IDR3, ODR3,
STR3, TWR0 to TWR15, SMIC, KCS, or BT
No address (LADR2) matches for IDR2, ODR2, or
STR2
No address (LADR1) matches for IDR1, ODR1, or
STR1
LPC3E
LPC2E
LPC1E

Related parts for DF2166VT33