HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 83
HD64F3048VTF8
Manufacturer Part Number
HD64F3048VTF8
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3048F16.pdf
(907 pages)
Specifications of HD64F3048VTF8
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F3048VX8
- Current page: 83 of 907
- Download datasheet (6Mb)
2.8.2
In this state the CPU executes program instructions in normal sequence.
2.8.3
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Types and Priority
Priority
High
Low
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
Figure 2.12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
immediately after reset exception handling.
Program Execution State
Exception-Handling State
Type of
Exception
Reset
Interrupt
Trap instruction
Detection Timing
Synchronized with clock
End of instruction
execution or end of
exception handling*
When TRAPA instruction
is executed
Rev. 7.00 Sep 21, 2005 page 57 of 878
Start of Exception Handling
Exception handling starts immediately
when RES changes from low to high
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Exception handling starts when a trap
(TRAPA) instruction is executed
REJ09B0259-0700
Section 2 CPU
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