DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 317
![MCU 5V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2345TE20
Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2345TE20V.pdf
(929 pages)
Specifications of DF2345TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20
HD64F2345TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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9.2.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers
are initialized to H'C0 by a reset, and in hardware standby mode.
Note: Make TMDR settings only when TCNT operation is stopped.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and
cannot be modified.
Bit 5
BFB
0
1
Channel 0: TMDR0
Channel 3: TMDR3
Bit
Initial value
R/W
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Bit
Initial value
R/W
Timer Mode Register (TMDR)
Description
TGRB operates normally
TGRB and TGRD used together for buffer operation
:
:
:
:
:
:
—
—
—
—
7
1
7
1
—
—
—
—
6
1
6
1
BFB
R/W
—
—
5
0
5
0
BFA
R/W
—
—
4
0
4
0
Rev. 4.00 Feb 15, 2006 page 291 of 900
Section 9 16-Bit Timer Pulse Unit (TPU)
MD3
MD3
R/W
R/W
3
0
3
0
MD2
MD2
R/W
R/W
2
0
2
0
REJ09B0291-0400
MD1
MD1
R/W
R/W
1
0
1
0
(Initial value)
MD0
MD0
R/W
R/W
0
0
0
0
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