HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 64
HD6473228F10V
Manufacturer Part Number
HD6473228F10V
Description
MCU 5V 32K,PB-FREE 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheet
1.HD6413238F10.pdf
(301 pages)
Specifications of HD6473228F10V
Core Processor
H8/300
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Peripherals
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473228F10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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3.6.1 Program Execution State
In this state the CPU executes program instructions in sequence. The main program, subroutines,
and interrupt-handling routines are all executed in this state.
3.6.2 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or accepts an
interrupt. In this state the CPU carries out a hardware-controlled sequence that prepares it to
execute a user-coded exception-handling routine.
In the hardware exception-handling sequence the CPU does the following:
See section 4, “Exception Handling,” for further information on the exception-handling state.
(1)
(2)
(3)
(4)
Notes:
1. A transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode.
2. A transition from any state to the hardware standby mode occurs when STBY goes Low.
Saves the program counter and condition code register to the stack (except in the case of a
reset).
Sets the interrupt mask (I) bit in the condition code register to “1.”
Fetches the start address of the exception-handling routine from the vector table.
Branches to that address, returning to the program execution state.
RES = 1
Exception -
handling state
Reset state
Interrupt
request
STBY=1 or RES=0
NMI or IRQ
to IRQ
strobe interrupt
Exception
handling
Interrupt request
Program
execution state
Figure 3-12. State Transitions
2
input
0
55
SLEEP
instruction
Power-down state
Sleep mode
Software
standby mode
Hardware
standby mode
Fig. 3-12
SLEEP instruction
with SSBY bit set
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