HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 138
HD6473228F10V
Manufacturer Part Number
HD6473228F10V
Description
MCU 5V 32K,PB-FREE 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheet
1.HD6413238F10.pdf
(301 pages)
Specifications of HD6473228F10V
Core Processor
H8/300
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Peripherals
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473228F10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 2
OEA
0
1
Bits 1 and 0 – Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
Bit 1
CKS1
0
0
1
1
7.2.5 Timer Control/Status Register (TCSR) – H’FF91
Bit
Initial value
Read/Write
* Software can write a 0 in bits 7 to 4 to clear the flags, but cannot write a 1 in these bits.
The TCSR is an 8-bit readable and partially writable register that contains the four interrupt flags
and selects the output compare levels, input capture edge, and whether to clear the counter on
compare-match A.
The TCSR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – Input Capture Flag (ICF): This status bit is set to 1 to flag an input capture event,
indicating that the FRC value has been copied to the ICR.
ICF must be cleared by software. It is set by hardware, however, and cannot be set by software.
Description
Output compare A output is disabled.
Output compare A output is enabled.
Bit 0
CKS0
0
1
0
1
R/(W)* R/(W)* R/(W)* R/(W)*
ICF
7
0
Description
Ø/2 Internal clock source
Ø/8 Internal clock source
Ø/32 Internal clock source
External clock source (rising edge)
OCFB
6
0
OCFA
5
0
OVF
130
4
0
OLVLB OLVLA
R/(W)
3
0
R/(W)
2
0
(Initial value)
(Initial value)
R/(W)
IEDG
1
0
CCLRA
R/W
0
0
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