HD64F2239FA16 Renesas Electronics America, HD64F2239FA16 Datasheet - Page 534

• Manufacturer Part Number: HD64F2239FA16
• Description: IC H8S MCU FLASH 384K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239FA16

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 13 Watchdog Timer (WDT)
13.3.3
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
and not by the WDT internal reset signal caused by overflows.
Note:
Rev. 6.00 Mar. 18, 2010 Page 472 of 982
REJ09B0054-0600
Bit
7
6
5
4 to 0
* Only 0 can be written, to clear the flag.
Reset Control/Status Register (RSTCSR) (only WDT_0)
Bit Name
WOVF
RSTE
RSTS
⎯
Initial
Value
0
0
0
All 1
R/W
R/(W) *
R/W
R/W
⎯
Description
Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written, to clear the flag.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
Reset Enable
Specifies whether or not a reset signal is
generated in the chip if TCNT overflows during
watchdog timer operation.
0: Reset signal is not generated even if TCNT
1: Reset signal is generated if TCNT overflows
Reset Select
This bit selects the type of the internal reset that is
generated by TCNT overflowing in watchdog timer
mode.
0: Power-on reset
1: Manual reset
Reserved
These bits are always read as 1 and cannot be
modified.
overflows (Though this LSI is not reset, TCNT
and TCSR in WDT are reset)