DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 487

• Manufacturer Part Number: DF71241D50FPV
• Description: MCU RISC FLASH 5V 32K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71241D50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4.5
Figure 12.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SCSSR to 0 before transmission. Note that the MPBT bit must be
held 1 until when an ID is transmitted. All other SCI operations are the same as those in
asynchronous mode.
Multiprocessor Serial Data Transmission
Figure 12.16 Sample Multiprocessor Serial Transmission Flowchart
Write transmit data to SCTDR and
as an output port with the PFC
Clear TE bit in SCSCR to 0;
Read TDRE flag in SCSSR
Read TEND flag in SCSSR
set MPBT bit in SCSSR
Clear TDRE flag to 0
All data transmitted?
Clear SPBODT to 0
select the TXD pin
Start transmission
Break output?
Initialization
TDRE = 1?
TEND = 1?
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
SCI initialization:
Set the TXD pin using the PFC.
After the TE bit is set to 1, 1 is output
for one frame, and transmission is
enabled. However, data is not
transmitted.
SCI status check and transmit data
write:
Read SCSSR and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR. Set the
MPBT bit in SCSSR to 0 or 1. Finally,
clear the TDRE flag to 0.
After initializing the SCI, when an ID
is written to SCTDR register so as to
transmit the ID, data is immediately
transferred, and then the TDER flag is
set to 1. The MPBT bit must be held 1
because the ID is not transmitted from
the TXD pin at this time. When the
TDRE flag is set to 1 after data
following the ID is written to SCTDR,
clear the MPBT bit to 0.
Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to SCTDR, and then clear
the TDRE flag to 0.
Break output at the end of serial
transmission:
To output a break during serial
transmission, first clear the SPBODT
bit in the serial port register
(SCSPTR) to 0, then clear the TE bit
in SCSCR to 0 and use the PFC to
select the TXD pin as an output port.
Rev. 5.00 Mar. 06, 2009 Page 467 of 770
REJ09B0243-0500