DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 476

MCU RISC FLASH 5V 32K 48-LQFP

DF71241D50FPV

Manufacturer Part Number
DF71241D50FPV
Description
MCU RISC FLASH 5V 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71241D50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71241D50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.4.3
In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver are independent, so full-duplex communication is possible while
sharing the same clock. Both the transmitter and receiver have a double-buffered structure so that
data can be read or written during transmission or reception, enabling continuous data transfer.
Figure 12.8 shows the general format in clock synchronous serial communication.
Rev. 5.00 Mar. 06, 2009 Page 456 of 770
REJ09B0243-0500
Figure 12.7 shows an example of the operation for reception.
Serial
data
RDRF
FER
Clock Synchronous Mode (Channel 1 in the SH7124 is not Available)
Synchronization
clock
Serial data
Note: * High level except in continuous transfer
1
Figure 12.8 Data Format in Clock Synchronous Communication
Start
bit
0
Don't care
Figure 12.7 Example of SCI Receive Operation
D0
*
D1
One frame
(8-Bit Data, Parity, One Stop Bit)
LSB
Bit 0
Data
D7
One unit of transfer data (character or frame)
Bit 1
RXI interrupt
request
Parity
bit
0/1
Bit 2
Stop
bit
1
Start
bit
Bit 3
0
Data read and RDRF flag
cleared to 0 by RXI
interrupt handler
D0
Bit 4
D1
Data
Bit 5
D7
Bit 6
Parity
bit
0/1
MSB
Stop
bit
ERI interrupt request
generated by framing
error
Bit 7
1
Don't care
*
0/1

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