DF71241D50FPV Renesas Electronics America, DF71241D50FPV Datasheet - Page 448
![MCU RISC FLASH 5V 32K 48-LQFP](/photos/28/61/286106/48-lqfp__plqp0048ja-a_sml.jpg)
DF71241D50FPV
Manufacturer Part Number
DF71241D50FPV
Description
MCU RISC FLASH 5V 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71241D50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71241D50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 448 of 794
- Download datasheet (5Mb)
Rev. 5.00 Mar. 06, 2009 Page 428 of 770
REJ09B0243-0500
Bit
3
Bit Name
PER
Initial
value
0
R/W
R/(W)* Parity Error
Description
Indicates that a parity error occurred during data
reception in asynchronous mode, causing abnormal
termination.
0: Indicates that reception is in progress or was
[Clearing conditions]
•
•
1: Indicates that a parity error occurred during
[Setting condition]
•
Notes: 1. The PER flag is not affected and retains
completed successfully*
reception*
By a power-on reset or in standby mode
When 0 is written to PER after reading PER = 1
When the number of 1s in the received data and
parity does not match the even or odd parity
specified by the O/E bit in the serial mode register
(SCSMR).
2. If a parity error occurs, the receive data is
its previous value when the RE bit in
SCSCR is cleared to 0.
transferred to SCRDR but the RDRF flag
is not set. Subsequent serial reception
cannot be continued while the PER flag is
set to 1.
2
1
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