MC908AZ60AVFUER Freescale Semiconductor, MC908AZ60AVFUER Datasheet - Page 39

• Manufacturer Part Number: MC908AZ60AVFUER
• Description: IC MCU 64K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2 I/O Section
Addresses $0000–$004F, shown in
Freescale Semiconductor
Addr.
$000A
$000B
$000C
$000D
$000E
$000F
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Data Direction Register G
Data Direction Register C
Data Direction Register D
Data Direction Register H
Data Direction Register A
Data Direction Register B
Data Direction Register E
Data Direction Register F
Register Name
Port C Data Register
Port D Data Register
Port G Data Register
Port H Data Register
Port A Data Register
Port B Data Register
Port E Data Register
Port F Data Register
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Figure 2-2. I/O Data, Status and Control Registers (Sheet 1 of 5)
(DDRG)
(DDRA)
(DDRB)
(DDRC)
(DDRD)
(DDRE)
(DDRH)
(DDRF)
(PTG)
(PTB)
(PTC)
(PTD)
(PTE)
(PTH)
(PTF)
(PTA)
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
MCLKEN
Figure
DDRA7
DDRB7
DDRD7
DDRE7
Bit 7
PTB7
PTD7
PTE7
PTA7
R
R
R
R
R
R
R
0
0
0
0
0
0
0
2-2, contain the I/O Data, Status, and Control Registers.
= Unimplemented
DDRA6
DDRB6
DDRD6
DDRE6
DDRF6
PTB6
PTD6
PTE6
PTF6
PTA6
6
R
R
R
R
R
R
0
0
0
0
0
0
DDRC5
DDRD5
DDRA5
DDRB5
DDRE5
DDRF5
PTB5
PTC5
PTD5
PTE5
PTA5
PTF5
5
R
R
R
R
0
0
0
0
DDRC4
DDRD4
DDRA4
DDRB4
DDRE4
DDRF4
PTB4
PTC4
PTD4
PTE4
PTA4
PTF4
R
R
R
R
4
0
0
0
0
DDRA3
DDRB3
DDRC3
DDRD3
DDRE3
DDRF3
PTB3
PTC3
PTD3
PTE3
PTA3
PTF3
R
R
R
R
R
3
0
0
0
0
= Reserved
DDRG2
DDRA2
DDRB2
DDRC2
DDRE2
DDRF2
DDR2
PTC2
PTD2
PTG2
PTA2
PTB2
PTE2
PTF2
2
R
R
0
0
DDRA1
DDRB1
DDRC1
DDRD1
DDRE1
DDRG1
DDRH1
DDRF1
PTC1
PTD1
PTG1
PTH1
PTB1
PTE1
PTF1
PTA1
1
I/O Section
DDRA0
DDRB0
DDRC0
DDRD0
DDRE0
DDRG0
DDRH0
DDRF0
Bit 0
PTG0
PTB0
PTC0
PTD0
PTE0
PTF0
PTH0
PTA0
39