MC908AZ60AVFUER Freescale Semiconductor, MC908AZ60AVFUER Datasheet - Page 346

• Manufacturer Part Number: MC908AZ60AVFUER
• Description: IC MCU 64K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
Valid Passive Logic 0
Valid Passive Logic 1
Valid EOD Symbol
Valid EOF and IFS Symbol
Idle Bus
Invalid Active Bit
346
See
occurs between a and b, the current bit would be considered a logic 0.
See
occurs between b and c, the current bit would be considered a logic 1.
See
occurs between c and d, the current symbol would be considered a valid end-of-data symbol (EOD).
In
message occurs between a and b, the current symbol will be considered a valid end-of-frame (EOF)
symbol.
See
message occurs between c and d, the current symbol will be considered a valid EOF symbol followed
by a valid inter-frame separation symbol (IFS). All nodes must wait until a valid IFS symbol time has
expired before beginning transmission. However, due to variations in clock frequencies and bus
loading, some nodes may recognize a valid IFS symbol before others and immediately begin
transmitting. Therefore, any time a node waiting to transmit detects a passive-to-active transition once
a valid EOF has been detected, it should immediately begin transmission, initiating the arbitration
process.
In
symbol of the next message does not occur before d, the bus is considered to be idle, and any node
wishing to transmit a message may do so immediately.
In
occurs between the passive-to-active transition beginning the current data bit (or symbol) and a, the
current bit would be invalid.
Figure 27-8
Figure 27-8
Figure 27-9
Figure 27-7
Figure 27-7
Figure 27-7
Figure 27-8
ACTIVE
PASSIVE
ACTIVE
PASSIVE
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
(1), if the passive-to-active received transition beginning the SOF symbol of the next
(2), if the passive-to-active received transition beginning the start-of-frame (SOF)
(1), if the active-to-passive received transition beginning the next data bit (or symbol)
(2). If the passive-to-active received transition beginning the next data bit (or symbol)
(3). If the passive-to-active received transition beginning the next data bit (or symbol)
(4). If the passive-to-active received transition beginning the next data bit (or symbol)
(2). If the passive-to-active received transition beginning the SOF symbol of the next
Figure 27-8. J1850 VPW Received Passive
280 μs
EOF and IFS Symbol Times
300 μs
a
b
c
d
(1) VALID EOF SYMBOL
(2) VALID EOF+
IFS SYMBOL
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