MC908AZ60AVFUER Freescale Semiconductor, MC908AZ60AVFUER Datasheet - Page 347

• Manufacturer Part Number: MC908AZ60AVFUER
• Description: IC MCU 64K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Valid Active Logic 1
Valid Active Logic 0
Valid SOF Symbol
Valid BREAK Symbol
Freescale Semiconductor
In
occurs between a and b, the current bit would be considered a logic 1.
In
occurs between b and c, the current bit would be considered a logic 0.
In
occurs between c and d, the current symbol would be considered a valid SOF symbol.
In
symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be transmitted onto the J1850 bus. See
J1850 Frame Format for BDLC response to BREAK symbols.
Figure
Figure 27-9
Figure 27-9
Figure 27-9
27-10, if the next active-to-passive received transition does not occur until after e, the current
PASSIVE
PASSIVE
PASSIVE
PASSIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
(2), if the active-to-passive received transition beginning the next data bit (or symbol)
(3), if the active-to-passive received transition beginning the next data bit (or symbol)
(4), if the active-to-passive received transition beginning the next data bit (or symbol)
Figure 27-9. J1850 VPW Received Active Symbol Times
64 μs
a
a
128 μs
200 μs
b
b
c
c
d
(1) INVALID ACTIVE BIT
(2) VALID ACTIVE LOGIC 1
(3) VALID ACTIVE LOGIC 0
(4) VALID SOF SYMBOL
BDLC MUX Interface
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