MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 6

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Signal Description
3
This chapter describes the MCF5253 input and output signals. The signal descriptions as shown in
are grouped according to relevant functionality. For additional signal information, see “Chapter 2, Signal
Description” in the MCF5253 reference manual.
6
UART
USBOTG
Mnemonic
Address
Read-write control
Output enable
Data
Synchronous row
address strobe
Synchronous column
address strobe
SDRAM write enable
SDRAM upper byte
enable
SDRAM lower byte
enable
SDRAM chip selects
SDRAM clock enable
System clock
Block
Signal Name
Signal Description
Universal
Asynchronous
Receiver
/Transmitter Module
USB 2.0 High-Speed
On-The-Go
Block Name
A[24:1]
A[23]/GPO54
RW
OE
D[31:16]
SDRAS/GPIO59
SDCAS/GPIO39
SDWE/GPIO38
SDUDQM/GPO53
SDLDQM/GPO52
SD_CS0/GPIO60
BCLKE/GPIO63
BCLK/GPIO40
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4
Table 2. Digital and Analog Modules (continued)
Connectivity
Peripheral
Connectivity
Peripheral
Functional
Grouping
Mnemonic
Table 3. MCF5253 Signal Index
Three UARTs handle asynchronous serial communication.
The USB module is used for communication to a PC or communication to
slave devices; for example, to download data from a hard disc player to a
flash player, and to other devices.
Bus write enable—indicates if read
Data bus used to transfer word data
Column address strobe for external
Write enable for external SDRAM
Upper byte enable—indicates during
Lower byte enable—indicates during
write cycle if low byte is written.
SDRAM chip select
24 address lines—address 23 is
multiplexed with GPO54 and
address 24 is multiplexed with A20
(SDRAM access only).
or write cycle in progress.
Output enable for asynchronous
memories connected to chip selects
Row address strobe for external
SDRAM
SDRAM
write cycle if high byte is written.
SDRAM clock enable
SDRAM clock output
Function
Brief Description
Freescale Semiconductor
Output
Input/
In/Out
In/Out
In/Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
negated
negated
negated
negated
negated
Table 3
Reset
State
Hi-Z
X
H
–
–
–
–