MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 19

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5
Table 18
later time.
6
This section includes the pin assignment information, contact connection diagram, and the mechanical
package drawing.
Freescale Semiconductor
J2A
J2B
J3A
J3B
J10
J11
J12
ID
J1
J4
J5
J6
J7
J8
J9
–
Power Consumption
Package Information and Pinout
shows maximum power consumption for the MCF5253 device. Typicals will be supplied at a
TCK Frequency of Operation
TCK Cycle Time
TCK Clock Pulse High Width
TCK Clock Pulse Low Width
TCK Fall Time (V
TCK Rise Time (V
TDI, TMS to TCK rising (Input Setup)
TCK rising to TDI, TMS Invalid (Hold)
Boundary Scan Data Valid to TCK (Setup)
TCK to Boundary Scan Data Invalid to rising edge (Hold)
TRST Pulse Width (asynchronous to clock edges)
TCK falling to TDO Valid (signal from driven or three-state)
TCK falling to TDO High Impedance
TCK falling to Boundary Scan Data Valid (signal from driven or three-state)
TCK falling to Boundary Scan. Data High Impedance
1
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4
IH
(with core supplied via internal 1.2 V regulator
IL
=2.4 V to V
This does not include the current required for any externally
connected 3.3V device (e.g., flash, SDRAM, and other I/O
devices).
=0.5 v to V
which is fed from the 3.3 V supply)
(with core supplied separately)
Table 18. Maximum Power Consumption
IL
IH
Table 17. JTAG Timing Parameters
=0.5 V)
=2.4 V)
Characteristic
1.2 V Core
3.3 V I/O
3.3 V I/O
Supply
Maximum Current
150 mA
150 mA
400 mA
1
Min
100
25
25
10
10
12
—
—
—
—
0
8
1
2
1
Power Consumption
Max
10
15
15
—
—
—
—
—
—
—
—
15
15
5
5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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