MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 10

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Signal Description
10
QSPI data out
QSPI chip selects
System oscillator in
System oscillator out
Reset In
Freescale Test Mode
Linear regulator output
Linear regulator input
Linear regulator ground LINGND
High Impedance
Debug Data
Processor Status
Processor clock
Test Clock
Test Reset/
Development Serial
Clock
Test Mode Select/Break
Point
Test Data Input/
Development Serial
Input
Test Data
Output/Development
Serial Output
Signal Name
RCK/QSPIDIN/QSPIDOUT/GPIO26
QSPIDOUT/SFSY/GPIO27
QSPICS0/EBUIN4/GPIO15
QSPICS1/EBUOUT2/GPIO16
QSPICS2/MCLK2/GPIO24
CS1/QSPICS3/GPIO28
CRIN
CROUT
RSTI
TEST[2:0]
LINOUT
LININ
HI_Z
DDATA0/CTS1/SDATA0_SDIO1/GPIO1
DDATA1/RTS1/SDATA2_BS2/GPIO2
DDATA2/CTS0/GPIO3
DDATA3/RTS0/GPIO4
PST0/GPIO50
PST1/GPIO49
PST2/INTMON2/GPIO48
PST3/INTMON1/GPIO47
PSTCLK/GPIO51
TCK
DSCLK/TRST
TMS/BKPT
TDI/DSI
TDO/DSO
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4
Table 3. MCF5253 Signal Index (continued)
Mnemonic
System input
System output
TEST pins.
Output of 1.2 V to supply core
Multiplexed serial input for the JTAG
Multiplexed serial output for the
QSPI data out
QSPI chip selects
Processor reset input
Input, typically I/O supply (3.3V)
Assertion tri-states output signal pins
Display of captured processor data
and break-point statuses
Indication of internal processor
status.
Processor clock output
Clock signal for IEEE 1149.1A JTAG
Multiplexed signal that is
asynchronous reset for JTAG
controller. Also, clock input for debug
module.
Multiplexed signal that is test mode
select in JTAG mode and a hardware
break-point in debug mode
or background debug module.
JTAG or background debug module
Function
Freescale Semiconductor
Output
Input/
In/Out
In/Out
In/Out
In/Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
In
Reset
State
Hi-Z
Hi-Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–