HD64F3687GFP Renesas Electronics America, HD64F3687GFP Datasheet - Page 76
![IC H8 MCU FLASH 56K 64-LQFP](/photos/28/61/286107/64-lqfp__plqp0064kc-a_sml.jpg)
HD64F3687GFP
Manufacturer Part Number
HD64F3687GFP
Description
IC H8 MCU FLASH 56K 64-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3684GFPV.pdf
(538 pages)
Specifications of HD64F3687GFP
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 2 CPU
Bit manipulation for two registers assigned to the same address
Example 1: Bit manipulation for the timer load register and timer counter
(Applicable for timer B1 in the H8/3687 Group.)
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit-manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Example 2: The BSET instruction is executed for port 5.
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
Rev.5.00 Nov. 02, 2005 Page 42 of 500
REJ09B0027-0500
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Count clock
Timer load register
Timer counter
Address
Reload
Read
Write
Internal data bus
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