HD64F3687GFP Renesas Electronics America, HD64F3687GFP Datasheet - Page 389
![IC H8 MCU FLASH 56K 64-LQFP](/photos/28/61/286107/64-lqfp__plqp0064kc-a_sml.jpg)
HD64F3687GFP
Manufacturer Part Number
HD64F3687GFP
Description
IC H8 MCU FLASH 56K 64-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3684GFPV.pdf
(538 pages)
Specifications of HD64F3687GFP
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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2. Page Write
SDA
SCL
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
This LSI is capable of the page write operation which allows any number of bytes up to 8 bytes
to be written in a single write cycle. The write data is input in the same sequence as the byte
write in the order of a start condition, slave address + R/W code, memory address (n), and
write data (Dn) with every ninth bit acknowledgement "0" output. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) is input instead of
receiving a stop condition after receiving the write data (Dn). LSB 3 bits (A2 to A0) in the
EEPROM address are automatically incremented to be the (n+1) address upon receiving write
data (Dn+1). Thus the write data can be received sequentially.
Addresses in the page are incremented at each receipt of the write data and the write data can
be input up to 8 bytes. If the LSB 3 bits (A2 to A0) in the EEPROM address reach the last
address of the page, the address will roll over to the first address of the same page. When the
address is rolled over, write data is received twice or more to the same address, however, the
last received data is valid. At the receipt of the stop condition, write data reception is
terminated and the write operation is entered.
The page write operation is shown in figure 19.4.
condition
Start
1
2
3
Slave address
4
5
Figure 19.3 Byte Write Operation
6
7
R/W ACK
8
9
A15
1
Upper memory
address
A8
8
ACK
9
A7
Rev.5.00 Nov. 02, 2005 Page 355 of 500
1
lower memory
address
A0
8
ACK
9
D7
1
Write Data
Section 19 EEPROM
REJ09B0027-0500
D0
8
ACK
9
conditon
Stop
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