HD64F3687GFP Renesas Electronics America, HD64F3687GFP Datasheet - Page 45
![IC H8 MCU FLASH 56K 64-LQFP](/photos/28/61/286107/64-lqfp__plqp0064kc-a_sml.jpg)
HD64F3687GFP
Manufacturer Part Number
HD64F3687GFP
Description
IC H8 MCU FLASH 56K 64-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3684GFPV.pdf
(538 pages)
Specifications of HD64F3687GFP
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3687GFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD64F3687GFPMV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD64F3687GFPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with
the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space.
CPU30H2C_000120030300
Upward-compatible with H8/300 CPUs
General-register architecture
Sixty-two basic instructions
Eight addressing modes
64-kbyte address space
High-speed operation
Power-down state
Can execute H8/300 CPUs object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added.
Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit
registers, or eight 32-bit registers
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract
8 8-bit register-register multiply
16 ÷ 8-bit register-register divide
16 16-bit register-register multiply : 22 states
32 ÷ 16-bit register-register divide
Transition to power-down state by SLEEP instruction
Section 2 CPU
: 14 states
: 14 states
: 22 states
: 2 state
Rev.5.00 Nov. 02, 2005 Page 11 of 500
REJ09B0027-0500
Section 2 CPU
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