MCF5329CVM240J Freescale Semiconductor, MCF5329CVM240J Datasheet - Page 37

• Manufacturer Part Number: MCF5329CVM240J
• Description: IC MPU RISC 240MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF5329CVM240J

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Family Name: MPC5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 240MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Processor Series: MCF532xx
• Core: ColdFire V3
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.15
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
5.15.1
The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_RXCLK frequency.
Table 23
Figure 23
5.15.2
Table 24
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_TXCLK frequency.
Figure 24
Freescale Semiconductor
Num
Num
M5
M6
M7
M8
M1
M2
M3
M4
FEC_RXD[3:0] (inputs)
lists MII receive channel timings.
lists MII transmit channel timings.
shows MII receive signal timings listed in
shows MII transmit signal timings listed in
FEC_RXCLK (input)
Fast Ethernet AC Timing Specifications
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid
FEC_TXCLK pulse width high
FEC_TXCLK pulse width low
MII Receive Signal Timing
MII Transmit Signal Timing
FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup
FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold
FEC_RXCLK pulse width high
FEC_RXCLK pulse width low
FEC_RXER
FEC_RXDV
MCF532x ColdFire
Figure 23. MII Receive Signal Timing Diagram
Characteristic
Characteristic
Table 24. MII Transmit Signal Timing
Table 23. MII Receive Signal Timing
M1
Table
®
Table
Microprocessor Data Sheet, Rev. 5
M2
23.
24.
M3
M4
35%
35%
35%
35%
Min
Min
—
5
5
5
65%
65%
Max
Max
65%
65%
25
—
—
—
Electrical Characteristics
FEC_RXCLK period
FEC_RXCLK period
FEC_TXCLK period
FEC_TXCLK period
Unit
Unit
ns
ns
ns
ns
37